Addl2a r0,r1, Rx2 + Rx → Rx | Freescale Semiconductor SC140 specs

ADDL2A

ADDL2A Add With Two-Bit Arithmetic Shift Left ADDL2A
	of Source Operand (AGU)
Operation	Assembler Syntax
(rx<<2) + Rx → Rx	ADDL2A rx,Rx

Description

ADDL2A rx,Rx

Performs a two-bit arithmetic shift left on the data from AGU source register (rx), adds the result to another AGU source register (Rx), and stores the sum in the destination (second) register (Rx). For R0-R7 destinations, the operation is affected by the modifier mode selected in MCTL.

Status and Conditions that Affect Instruction

Register Address	Bit Name	Description
SR[18]	EXP	Determines which stack pointer is used when the stack pointer is an
		operand. Otherwise, the instruction is not affected by SR.
MCTL[31:0]	AM3–AM0	Address modification bits when updating R0–R7. Otherwise, the
		instruction is not affected by MCTL.

Status and Conditions Changed by Instruction

None.

Example

addl2a r0,r1

Register/Memory Address

MCTL

Before

$0000 0000

$0000 0055

$0000 0011

After

$0000 0165

In binary:

R0 shifted left two

Sum

01010101

101010101

00010001

101100101

A-34	SC140 DSP Core Reference Manual

Page 348

Image 348

Freescale Semiconductor SC140 ADDL2A Add With Two-Bit Arithmetic Shift Left ADDL2A, Addl2a r0,r1, Rx2 + Rx → Rx

Contents

SC140 DSP Core Reference Manual SC140 DSP Core Reference Manual Table of Contents SC140 DSP Core Reference Manual Control Registers SC140 DSP Core Reference Manual Program Control Instruction Set Accelerator Plug-In Programming Rules SC140 DSP Core Instruction Set Appendix a StarCore Registry Appendix B Xii List of Figures Xiv List of Tables Xvi SC140 DSP Core Reference Manual Xvii Xviii List of Examples SC140 DSP Core Reference Manual SC140 DSP Core Reference Manual Xxi Xxii About This Book Abbreviations used in this manual are listed below AbbreviationsAbbreviation Description ISR Revision History Revision Date Description Chapter Introduction Target Markets Architectural Differentiation Core Architecture Features Typical System-On-Chip Configuration Variable Length Execution Set Vles Software Model SoC DSP expansion areaSystem expansion area SC140 platform Core Architecture Features Chapter Core Architecture Architecture Overview Block Diagram of the SC140 Core Data Arithmetic Logic Unit Dalu Address Generation Unit AGU Data Register FileMultiply-Accumulate MAC Unit Bit-Field Unit BFU Stack Pointer Registers Bit Mask Unit BMU Program Sequencer Unit Pseq Enhanced On-Chip Emulator EOnCEInstruction Set Accelerator Plug-in Isap Interface Memory Interface Dalu Dalu Architecture Dalu Programming Model Limit EXT Data Registers D0-D15 Write to Data Registers Read from Data RegistersOperand Type Dn.e Dn.h Dn.l Data Registers Access Width Dalu Arithmetic Instructions MACOperand Type Data Width Bits Instruction Description DIV NEG Data Shifter/Limiter Dalu Logical Instructions BFU Scaling LimitingCalculating the Ln Bit Scaling Example Scaling Mode Bits Defining the Ln bit Calculation Limiting with the Moves InstructionsLn Bit Calculation Scaling and Arithmetic Saturation Mode Interactions Selected Special Six Other Dalu Instructions ModeLimiting Example 10. Scaling and Limiting Interactions Dalu Arithmetic and Rounding Data Representation11. Saturation and Rounding Interactions Data Formats Signed Fractional Signed Integer 12. Two’s Complement Word RepresentationsSigned Fractional Signed Integer Unsigned Integer Multiplication DivisionUnsigned Arithmetic Unsigned Multiplication 13. Rounding Position in Relation to Scaling Mode Scaling Mode High Portion Low PortionRounding Modes Unsigned Comparison Convergent Rounding No Scaling 2.6.2 Two’s Complement Rounding Two’s Complement Rounding No Scaling Arithmetic Saturation Mode 14. Arithmetic Saturation Example Multi-Precision Arithmetic Support Fractional Multi-Precision Arithmetic Fractional Double-Precision Multiplication Integer Multi-Precision Arithmetic Fractional Mixed-Precision Multiplication 10. Signed Integer Double-Precision Multiplication Viterbi Decoding Support 11. Unsigned Integer Double-Precision Multiplication Address Generation Unit AGU Architecture Address ArithmeticUnit AAU Address Generation Unit AGU Programming Model 13. AGU Programming Model Address Registers R0-R15 Stack Pointer Registers NSP, ESP Offset Registers N0-N3 Base Address Registers B0-B7Modifier Registers M0-M3 Shadow Stack Pointer Registers Modifier Control Register Mctl 17. Address Modifier AM BitsAddress Modifier Modes Addressing Modes Register Direct ModesAddress Register Indirect Modes Address Generation Unit PC Relative Mode Special Addressing Modes Memory Access Width Memory Access Misalignment Access Type Aligned Address Addressing Modes Summary19. Memory Address Alignment 20. Addressing Modes Summary Address Register Indirect PC RelativeSpecial Linear Addressing Mode Reverse-carry Addressing ModeModulo Addressing Mode Address Modifier Modes 15. Modulo Addressing Example Multiple Wrap-Around Modulo Addressing Mode 21. Modulo Register Values for Modulo Addressing ModeModifier Mj Address Calculation Arithmetic Arithmetic Instructions on Address Registers 23. AGU Arithmetic Instructions Bit Mask Instructions Bit Mask Test and Set Semaphore Support Instruction 24. AGU Bit Mask Instructions BMU Move Instructions Semaphore Hardware ImplementationExample of Normal Usage of the Semaphoring Mechanism Label BMTSET.W #mask,R0 JT label 25. AGU Move Instructions MOVE.W 16. Integer Move Instructions 17. Fractional Move Instructions Memory Interface 18. Bit Allocation in MOVE.L D0.eD1.e 1 SC140 Endian Support 1.1 SC140 Bus Structure Memory Organization 20. Basic Connection between SC140 Core and Memory Data Moves 26. Data Representation in MemoryRepresentation Type Value 22. Data Transfer in Big and Little Endian Modes Multi-Register Moves Address Data Multi-Register Transfer in Big and Little Endian Modes Instruction Word Transfers 25. Instruction Moves in Big and Little Endian Modes Memory Access Behavior in Big/Little Endian Modes Example MOVE.L D0.ED1.E, A0 Example MOVE.2L D0D1, R0Example MOVE.F D0, R0 Example MOVE.2F D0D1, R0 Example VSL.4W D2D6D1D3, R0 + N0 D6 =Example VSL.4F D2D6D1D3, R0 + N0 Example VSL.2W D1D3, R0 + N0 Example Push D0 Example Push D0 Push D1Example BMSET.W #$1234, A0 Data = 31. Control Instructions in Big and Little Endian Modes Instruction Register Operands Big Little Endian Core Control Registers Status Register SR Name Description Settings Describes the various SR bitsStatus Register Description I2-I0 Interrupt Mask Bits Reflect Exceptions Overflow Exception Enable Bit Disable Interrupts Bit When this bitException Mode Bit Selects Reserved Equation Mode S1-S0 Scaling Mode Bits SpecifyScaling Mode Bit Rounding Mode Bit Selects the type Name Description Settings Arithmetic Saturation Mode Selects Exception and Mode Register EMR Exception and Mode Register EMR Describes the EMR fields EMR Description Ilst Illegal Execution Set Indicates whether an PLL and Clock Registers Clearing EMR BitsBmclr #$fffb,EMR.L Example 3-1. Clearing an EMR Bit Emulation and Debug EOnCE Debugging System Jtag Interface Signal Descriptions Signal Name Signal DescriptionOverview of the Combined Jtag and EOnCE Interface Cascading Multiple SC140 EOnCE Modules in a SoC Jtag Scan Paths Jtag Instructions Loadgpr TAP Controller State Machine Jtag Scan Paths Select-DR Scan Path Select-IR Scan Path Activating the EOnCE Through the Jtag Port Enabling the EOnCE Module Debugrequest and Enableeonce Commands Reading/Writing EOnCE Registers Through Jtag Reading and Writing EOnCE Registers Via Jtag EOnCE register write operation through Jtag EOnCE register read capture operation through Jtag EOnCE Signals EOnCE Signals Jtag SignalsMain Capabilities of the EOnCE Module Core Interface EOnCE Dedicated Instructions Debug State Debug Exception Executing an Instruction while in Debug StateSoftware Downloading Software Downloading EOnCE Events EOnCE Event TypesEvent type Occurs when EOnCE Actions Event and Action SummaryEOnCE Event and Action Summary Event type EOnCE Enabling and Power Considerations EOnCE Module Internal ArchitectureEOnCE Controller Command Register Transmit Register Update Signal from the TAP ControllerAddress Monitor and Control Register Address Control Decoder Logic Receive Register Event Counter Shows a block diagram of the event counter Event Counter Register Set Event Detection Unit EDU EE5..0 Address BusesXDBxx Data Buses EventD Event0 Event1 Event2 Event5 Count event Address Event Detection Channel Edca EEi Edca Register Set Data Event Detection Channel Edcd Event External Event 6,7 Count EventEventD Edcd register set is shown below Event Selector ES Optional External Event Detection Address Channels EE40 ES block diagram is shown in Figure Trace UnitEvent0..Event5 External Event6, Event7 EventD Count event 10. Event Selector Register Set EOnCE Module Internal Architecture Change of Flow and Interrupt Tracing Change of FlowTrace Buffer TB Off-Core Writing to the Trace Buffer Reading the Trace Buffer TbbuffTrace Unit Programming Model EOnCE Register Addressing 11. Trace Buffer Register Set 12 displays the EOnCE register addressing offsets 12. EOnCE Register Addressing OffsetsOffset EDCA4REFA Reading or Writing EOnCE Registers Using Core Software Real-Time Jtag Access General EOnCE Register Issues Real-Time Data Transfer EOnCE Register Addressing EOnCE Command Register ECR Read/Write Command SpecifiesEOnCE Controller Registers 13 describes the ECR fields 16 displays the bit configuration of the ESR EOnCE Status Register ESR 14 describes the ESR fields 14. ESR DescriptionName Description Section DREE3 EOnCE Monitor and Control Register Emcr 15 describes the Emcr fields15. Emcr Description Name Description Reserved Debugerst EOnCE Receive Register Ercv EOnCE Transmit Register Etrsmt EE Signals EE Signals as OutputsDetection by the Event Detection Channels Detecting Entry into Debug State EE Signals as Inputs EE Signals Control Register Eectrl 16. Eectrl Description Eeddef EE2DEF Core Command Register Corecmd Length control bits are described in -17, below17. Length Control Bits Length Control Bits Description PC of the Exception Execution Set Pcexcp PC of the Next Execution Set PcnextPC of Last Execution Set Pclast PC Breakpoint Detection Register Pcdetect Event Counter Registers Event Counter Control Register Ecntctrl Extended Mode of Operation Bit 18 describes the Ecntctrl fields18. Ecntctrl Description Reserved for Test Event Counter Enable Used to Event Counter Value Register EcntvalEvents to be Counted Determines EC Signals Extension Counter Value Register Ecntext Event Detection Unit EDU Channels and Registers Address Event Detection Channel EdcaEdca Control Registers EDCAiCTRL 19 describes the EDCAiCTRL fields Event Detection Channel EDCAi Comparators Selection Used to Access Type Selection These bits Comparator B Condition SelectionComparator a Condition Selection Edca Reference Value Registers a and B EDCAiREFA, EDCAiREFB Edca Mask Register EDCAiMASK Data Event Detection Channel Edcd Edcd Control Register Edcdctrl20 describes the Edcdctrl fields 20. Edcdctrl Description Access Width Selection AWS Access Type Selection The ATS bit Comparator Condition Selection Event Selector ES Registers Event Selector Control Register EselctrlEdcd Reference Value Register Edcdref Edcd Mask Register Edcdmask Eselctrl fields are described in Table 21. Eselctrl Description 24 displays the bit configuration of Eseldm Event Selector Mask Debug State Register Eseldm Event Selector Mask Enable Trace Register Eseletb Event Selector Mask Debug Exception Register Eseldi Event Selector Mask Disable Trace Register Eseldtb Trace Unit RegistersTrace Buffer Control Register Tbctrl This mode is usefull only with the Tcount mode 22. Allowed tracing mode combinationsTrace mode Upon a trace event, trace the counter value Ecntval Trace Buffer Counter Mode Tbctrl fields are described in the following table23. Tbctrl Description Trace Buffer Extension Counter Trace Loops Mode Enables tracing Trace Buffer Enable Mode EnablesTrace Mark Instruction Mode Trace Issue of Execution Sets Enable Trace Buffer Read Pointer Register Tbrd Trace Buffer Write Pointer Register TbwrTrace Buffer Register Tbbuff Trace Unit Registers Chapter Program Control Pipeline Instruction Pipeline Stages Illustrates the five instruction pipeline stages Pipeline Example Pipeline Stages OverviewInstruction Cycle Operation Pipeline Stage Description Instruction Pre-Fetch and Fetch Instruction DispatchAddress Generation Instruction Grouping ExecutionExample 5-1. Four SC140 Instructions in an Execution Set Grouping Types Instruction Grouping Methods Serial Grouping Prefix Grouping Prefix Types Two-Word Prefix Conditional Execution One-Word Low Register PrefixFor example Prefix Instructions Assembly Syntax Meaning Prefix Selection Algorithm Low Register Prefix Selection Algorithm Instruction Reordering Within an Execution Set Example 5-4. Conditional Vles Having Two Subgroups Example 5-5. Set of 2 Two-word Instructions Requiring a NOP Instruction Timing Sequential Instruction Timing Instruction Categories Timing Summary Dalu Instruction Timing Move Instruction TimingBit Mask Instruction Timing Compare Shift Test Example 5-6. Delayed Change-of-Flow and Its Delay Slot Change-Of-Flow Instruction TimingNon-Loop Change-of-Flow Instructions Direct, PC-Relative, and Conditional COF Loop Change-Of-Flow Instructions Delayed COF COF Execution Cycles Example 5-7 shows a case when a stall cycle is added Highest cycle count of instructions grouped with CallNumber of Cycles Needed by Change-of-Flow Instructions Example 5-7. Subroutine Call Timing Memory Access Timing Memory Access Examples MOVE.L Example 5-8. Parallel Execution of Two Move Instructions Implicit Push/Pop Memory Timing Memory Stall Conditions Hardware Loops Loop Programming ModelLoop Start Address Registers SAn Loop Notation and Encoding Loop Counter Registers LCnStatus Register SR Loop Flag Bits Loop Initiation and Execution Lpmarka and Lpmarkb Bits in Short and Long LoopsLoop Type Location Functionality Loop Nesting Loop Iteration and Termination Loop Control Instructions 10 lists the loop instructions10. Loop Control Instructions Instruction Operation Example 5-13. Long Loop Disassembly Example 5-12. Long LoopExample 5-14. Short Loop, Two Execution Sets Following is an example of a nested loop Example 5-15. Short Loop, One Execution SetExample 5-16. Nested Loop Stack Support Loop Timing1 SC140 Single Stack Memory Use 2 SC140 Dual Stack Memory Use Shows the stack structure Stack Support Instructions 11. Stack Push/Pop Instructions12. Even and Odd Registers Even Register De File Odd Register Do File Addressing Mode Description Shadow Stack Pointer Registers13. Stack Memory Map 14. Stack Move Instructions Fast Return from Subroutines Normal Working Mode Exception Working ModeWorking Mode EXP bit Active SP Working Modes Typical Working Mode Usage Scenarios Dual-stack Rtos Working Mode Transitions From Exception to Normal modeFrom Normal to Exception mode Single-stack Rtos Working Modes Processing States Processing State Change Instructions16. Processing State Change Instructions 10. Core State Diagram Processing State Transitions Reset Processing State Execution State17. Processing State Transitions Processing State Transitions Description Wait Processing State Stop Processing State 18. Exit Wait Processing State due to an Interrupt or NMI Exception Processing SC140 11. Core-PIC Interface Interrupt Vector Address Vector Base Address RegisterProgramming Exception Routine Addresses Return From Exception Instructions 19. Exception Vector Address TableException Address Priority Type Description Offset Highest Maskable Interrupts Non-Maskable Interrupts NMIInternal Exceptions Interrupt Priority Level Illegal Exception Illegal InstructionIllegal Execution Set Exception Interface to the Pipeline Dalu OverflowTrap Exception Debug Exception Exception Mode Execution Exception Timing20. Exception Pipeline Example 5-17. Basic Exception Timing Exception Processing 12 provides a flow chart for Example 21. Pipeline Example Instruction Set Accelerator Plug-In Introduction Isap SC140 Schematic Connection Single IsapData Memory SC140Core Core to Multiple Isap Connection Schematic Multiple Isap Isap Memory Access Isap instructions and instruction encodingIsap Encoding Fields Binary Encoding Words Bits Example 6-1. Isap memory access ISAP-core register transfersTo understand this, look at the following lines of code Immediate Data Transfer to Isap registers Following line of codeExample 6-2. ISAP-Core register transfers Example 6-3. ISAP-Core register transfers Core Assembly Syntax with an Isap Identification of Isap instructionsWorking with One Isap Vles that uses an implicit Isap ID string Working with Multiple ISAPs One Isap in a Single-Line VlesOne Isap in a Multi-Line Vles An Example of the Definition Flexibility of an Isap Multiple ISAPs in a Multi-Line VlesExample 6-5. Multiple Isap coding Example 6-6. Conditional Execution Example Example 6-7. Conditional Execution Example Programming Rules Isap Functions that Interact With the Core Grouping rules for explicit Isap instructions Rules for implicit AGU instructions Sequencing rules for T bit update D.2, D.3 Programming Rules Vles Sequencing Semantics Vles Grouping Semantics Vles Grouping Semantics SC140 Pipeline Exposure Programming Rule NotationGrouping Rules Sequencing Rules Register Read/Write Status Bit Updates Instruction WordsMOVE-like Instructions Register Aliasing Delayed COF Instructions Delay SlotAGU Arithmetic Instructions Change-Of-Flow Destinations Enabled Loop Static Programming RulesHardware Loops Hardware Loop Detection General Grouping Rules Rule G.G.1Rule G.G.2 Rule G.G.3 Rule G.G.4 Example 7-5 Duplicate PC DestinationsExample 7-6 Duplicate Address Pointer Register Destinations Example 7-7 Duplicate Stack Pointer Destinations Rule G.G.4 Exceptions Example 7-8 Duplicate Register DestinationsExample 7-9 Duplicate SR/EMR Register Destinations Example 7-10 Duplicate Status Bit Destinations Prefix Grouping Rules Rule G.G.5Following rules only apply to prefix-grouped Vles Example 7-15. Dalu Register Use Exceeds Four Times Rule G.P.1 Example 7-16 Vles Extension Words Exceed TwoExample 7-17 Two-Word Instructions Exceed Two Rule G.P.3 Rule G.P.4Rule G.P.5 Example 7-18. Vles Has Mutually Exclusive Instructions Rule G.P.6 Rule G.P.7Example 7-20. Data Source Use of Nn and Mn Registers Example 7-21. IFc Having Two Subgroups Rule G.P.8 Rule G.P.9Example 7-24. Isap instructions in same IFc group AGU Rules Rule A.1Example 7-25. Mctl Write to R0-R7 Use Rule A.2 Rule A.3Example 7-26. Rn, Nn, Mn Write to AGU Use Rule A.4 Example 7-27. Rn or Nn Write to MOVE-like UseExample 7-28. LCn Write to MOVE-like Use Delayed COF Rules Example 7-29. Nmid Update to EMR ReadExample 7-30. Instructions in a Delay Slot Rule A.7 Example 7-31. Instructions in a Rted Delay Slot Example RTE/D with SR UpdatesRule D.2 Rule D.3 Rule D.4 Rule D.5Rule D.5a Rule D.6 Status Bit Rules Rule D.8Rule D.9 Rule T.1 Rule T.2.a Rule T.2.bRule T.2.c Rule SR.2 Static Programming Rules Example 7-43. SR Write to SR Status Bit Use Example 7-44. SR Write to SR Status Bit Update Rule SR.3Rule SR.4 Example 7-45. Dovf Update to SR Read or Write Example 7-46. Dovf Update grouped with Move-like SR updatesRule SR.4a Loop Nesting Rules Rule SR.7Rule L.N.1 DI and EI DOENn and DOENSHn Rule L.N.2 Rule L.N.3Example 7-49. Nested Loops with Ordered Index Example 7-50. Nested DOENn/DOENSHn Instructions Example 7-52. Loopend between Doen and Loopend Example 7-53. Changing a loop type Loop LA Rules Rule L.L.1Rule L.L.2 Example 7-54. Instructions at the End of Long Loops Rule L.L.3 Rule L.L.4LA of a short loop cannot be at LA-1 of a long loop Example 7-56. Instructions in Short Loops Loop Sequencing Rules Rule L.L.5Rule L.L.6 Rule L.D.1 Rule L.D.3 Rule L.D.5Rule L.D.6 Example 7-60. LCn Write at the Start of Short Loop n Rule L.D.7 Rule L.D.8Rule L.D.9 Loop COF Rules Rule L.C.1Rule L.C.2 Rule L.C.3 Rule L.C.5 Bc or Jc instruction is not allowed at LA-3 of a long loopExample 7-68. Bc/Jc at LA-3 of a Long Loop Rule L.C.7 Example 7-69. Loop COF Destination in the Same Loop Rule L.C.9 Rule L.C.10Example 7-70. Loop COF at End of Nested Long Loops Example 7-71. Subroutine Call to End of Loops General Looping Rules Rule L.C.11Rule L.C.12 Rule L.G.3 Dynamic Programming Rules AGU Dynamic RulesRule L.G.5 Rule A.2a Memory Access Rules Rule A.5Rule A.6 Rule D.7 RAS Rules Loop RulesRule J.4 Rule L.N.6 Example 7-83. A.2 from a Delay Slot to a COF Destination Rule Detection Across COF BoundariesCycle-Based COF Rules Example 7-82. SR.2 Across a COF Boundary VLES-Based COF Rules Example 7-85. EMR access at the start of an exception Rule Detection Across Exception BoundariesRule SR.2a Rule SR.4b Rule A.1a Example 7-86. Mctl Write to R0-R7 Use COF destination cannot be a delay slot Programming GuidelinesRule J.1 Rule J.2 Rules Not Detected Across COF Boundaries Good Programming PracticesSource Code Practices Rule J.5 Binary Code Practices Lpmark Rules Lpmark Instruction TypeSoftware Development Practices Static Programming Rules Dynamic Programming RulesGeneral Grouping Rules Prefix Grouping Rules Loop Nesting Rules Loop LA Rules Lpmark Rule L.L.2 Lpmark Rule L.L.3Lpmark Rule L.L.5 Example 7-93. Active LCn Write at the End of Long Loops Loop Sequencing Rules Lpmark Rule L.L.6Lpmark Rule L.D.2 + L.D.3 Lpmark Rule L.D.6 Loop COF Rules Lpmark Rule L.C.2COF instructions are not allowed at LPB of a long loop Example 7-97. Active LCn Read at the Start of a Loop Lpmark Rule L.C.3 + L.C.5 Example 7-98. COF Instructions at LPB of a Long LoopExample 7-99. Bc/Jc at the Start of a Loop Lpmark Rule L.C.9 Lpmark Rule L.C.10Example 7-100. Loop COF at End of Nested Long Loops Example 7-101. Subroutine Call to End of Loops Lpmark Programming Guidelines General Looping RulesRule Detection Across Exception Boundaries Example 7-104. COF Destination to Loop Delay Slots NOP DefinitionLpmark Rule L.C.1 Grouping Examples Is encoded as Is assembler mapped to the IFT prefix and encoded as Is assembler mapped to the IFF prefix and encoded as Is encoded ignoring the NOP subgroup as NOP Definition Appendix a SC140 DSP Core Instruction Set Conventions Table A-1. Instruction ConventionsConvention Definition Table A-2. Operations Syntax Table A-3. Register AbbreviationsOperator Description Abbreviation Register Name Brackets as Isap indicators Brackets as address indicatorsTable A-4. Assembler Syntax Addressing Mode Notation Table A-5. Addressing Mode Notation for the EA OperandTable A-6. Addressing Mode Notation for the ea Operand Addressing Mode Definition Notation in Instruction Field Data Representation in Memory for the Examples Encoding NotationDefinition for the field is Prefix Word Encoding Instruction Formats and Opcodes Instruction FieldsAaa Ccc Example, 2-w prefix + 2 grouped instruction words, aaa = If true D0, D2, A0, if false D1, D3, A1If true, all the set Prefix Words Cycles Type Last, or to last-1 Example First execution set of the loopHigh data register is used for the op3 field E3 is set High data register is used for the op1 field E2 is set DSP Core Instruction Set Instruction Types Instruction Sub-types Table A-7. Dalu Arithmetic Instructions MAC Table A-8. Dalu Logical Instructions BFU Table A-9. AGU Arithmetic Instructions Table A-10. AGU Move Instructions Table A-11. AGU Stack Support Instructions Table A-12. AGU Bit-Mask Instructions BMU Table A-13. AGU Non-Loop Change-of-Flow Instructions Table A-15. AGU Program Control Instructions Table A-16. Prefix Instructions Inst InstructionsInstruction Definition Layout ABS Single Source/Destination Data Register Instruction ADC Add Long With Carry DaluDc + Dd + C → Dd ADC Dc,Dd Dc,Dd Data Register Pairs Register/Memory Address Before ADD Add DaluOperation Assembler Syntax Add d0,d1,d2 Add d1,d0,d2 Da,Db Da,Da Data Register Pairs#u5 ADD2 Add Two 16-Bit Values DaluAdd2 d0,d1 JJJ Single Source Data Register Adda Add AGUAdda #u5,Rx Adda #s16,rx,Rn Adda r0,r1 Address Register Rrrr AGU Source Register AGU Source/Destination Register#s16 ADDL1A Add With One-Bit Arithmetic Shift Left ADDL1A Source Operand AGUAddl1a r0,r1 Rx1 + Rx → Rx ADDL1A rx,Rx ADDL2A Add With Two-Bit Arithmetic Shift Left ADDL2A Addl2a r0,r1Rx2 + Rx → Rx ADDL2A rx,Rx ADDL2A rx,Rx ADDNC.W Add Without Changing ADDNC.WCarry Bit Dalu Addnc.w #$ca3e,d1,d2 Instruction Words Cycles Type ADR Add and Round DaluAdr d3,d4 RndDa + Dn → Dn ADR Da,Dn Bitwise and Dalu #0u16,Da,Dn#u16$0000,Da,Dn Da,Dn D2,d1 #$0ff2e,d2,d1#$ff2e0000,d2,d1 #0u16 #u16$0000#u16 #$a70e,d1.h #u16 DR.L → DR.L#u16 DR.H → DR.H #u16,DR.L Data/Address Register Cycles Type Opcode AND.W #u16,Rn AND.W #u16,SP-u5AND.W #u16,a16 AND.W #u16,SP+s16 And.w #$54a1,r7 A16 S16 ASL Asl d0,d1Da 1→ Dn ASL Da,Dn ASL Da,Dn ASL2A Asl2a r0Rx2 → Rx ASL2A Rx Asla Asla r0Rx1 → Rx Asla Rx Asll Multiple-Bit Arithmetic Shift Left DaluAsll #u5,Dn Asll Da,Dn Asll d0,d1 Asll Aslw Word Arithmetic Shift Left 16 Bits Dalu AslwAslw d0,d1 Da16 → Dn Aslw Da,Dn ASR Asr d5,d3Da1 → Dn ASR Da,Dn Register/Memory Address Before After Asra Asra r2Asra Rx Asrr Multiple-Bit Arithmetic Shift Right Dalu Asrr #$3,d5 Asrr d3,d5 #u5 Asrw d5,d0 Asrw Da,Dn Asrw Da,Dn If T==0, then PC + displacement → PC Branch If False AGUBF lbl BF label Displacement label Instruction Words Cycles1 Type Opcode BFD Branch If False Using a Delay Slot AGU Operation BFDBFD lbl BFD label Label Displacement Bmchg ~C1.Hi → C1.Hi i denotes bits=1 in #u16~C1.Li → C1.Li ~DR.Hi → DR.Hi Bmchg #$f0f0,d1.h Clears the Ln bit in the destination data registerControl Registers Iiiiiiiiiiiiiiii 16-bit unsigned immediate data BMCHG.W Bit-Masked Change a Bmchg.w #$661f,$800c BMCHG.W #u16,SP-u5 Bit signed SP address offset Bmclr Bit-Masked Clear a 16-Bit Operand BMU Bmclr Operation Bmclr #u16,C1.HBmclr #u16,C1.L Bmclr #u16,DR.H Bmclr #$b646,d7.l #u16 BMCLR.W Bit-Masked Clear aBit Operand in Memory BMU Operation Assembler Syntax BMCLR.W #u16,SP-u5 Bmset #u16,C1.H Bmset #u16,C1.LBmset #u16,DR.H Bmset #u16,DR.L Bmset #$2436,d1.l BMSET.W Bit Operand in Memory BMU Bmset.w #$f111,$800c Register/Memory Address Before Immediate$800C Bmtset Bmtset #$111f,d1.lBmtset #u16,DR.H Bmtset #u16,DR.L Bmtset #$4238,d4.l BMTSET.W Bit-Masked Test and Set a BMTSET.W Bmtset.w #$4328,$c BMTSET.W #u16,SP-u5 Bmtstc Bmtstc #$8a59,d7.h $0$0024A60000 $00E40000 BMTSTC.W BMTSTC.W #u16,SP-u5BMTSTC.W #u16,SP+s16 BMTSTC.W #u16,Rn Bmtstc.w #$8A59,r0 BMTSTC.W #u16,SP-u5 Bmtsts Bmtsts #u16,C1.LBmtsts #u16,DR.H Bmtsts #u16,DR.L Bmtsts #$24a6,d7.h BMTSTS.W BMTSTS.W #u16,SP-u5BMTSTS.W #u16,SP+s16 BMTSTS.W #u16,Rn Bmtsts.w #$0428,r0 BMTSTS.W #u16,SP-u5 PC + displacement → PC BRABranch AGU BRA label AAAAAAAAAA0 Brad Brad labelSource Code Comments $0000 000A $0000 000E PC + displacement → PC BreakBreak label → LFn Encoding is the displacement with bit BSR Branch to Subroutine AGUStatus and Conditions Changed by Instruction None Example Bsr label BSR PC + displacement → PC, next* PC→RAS Next* PC → SP SR → SP + 4 SP + 8 → SPBsrd label Bsrd label If T==1, then PC + displacement → PC Branch If True AGUBT lbl BT label Register/Memory Address Before BT After BTD Branch If True Using a Delay Slot AGU Operation BTDBTD lbl BTD label $0035 $0000 $0006 $002A $001A $0016 CLB Count Leading Bits DaluClb d3,d7 CLB Da,Dn CLB Da,Dn CLR Clear a Data Register DaluClr d1 → Dn Destination Data Register Source Data Register Cmpeq Compare for Equal DaluCmpeq d2,d3 If Da == Dn, then 1→ T, else 0 → T 118 CMPEQ.W CMPEQ.W Compare for Equal DaluCmpeq.w #$5,d3 CMPEQ.W #u5,Dn CMPEQ.W Cmpeqa Compare for Equal AGU Cmpeqa Operation Cmpeqa r1,r2If rx == Rx, then 1 → T, else 0 → T Cmpeqa rx,Rx Cmpeqa rx,Rx Cmpgt Compare for Greater Than DaluCmpgt d2,d3 Dn Da → T 124 CMPGT.W Cmpgt.w #$8002,d2CMPGT.W #u5,Dn CMPGT.W #s16,Dn CMPGT.W #u5,Dn Cmpgta Compare for Greater Than AGU CmpgtaCmpgta r2,r3 Rx rx → T Cmpgta rx,Rx Cmphi Unsigned Compare for Higher Dalu CmphiCmphi d1,d0 Cmphi Da,Dn 130 Cmphia Unsigned Compare for Higher AGU CmphiaCmphia r0,r1 Cmphia rx,Rx Cmphia rx,Rx Cont Continue to the Next Loop Iteration AGULabel Label Cycles1 Type Opcode Contd Contd label Cycles1 Type Enter Debug Mode AGU DebugDebug Signal a Debug Event AGU Debugev Debugev Deca Decrement a Register AGUDeca r0 Rx 1 → Rx Bit unsigned immediate data = 1, set by the assembler Deceq d7 Dn 1 → Dn if Dn==0, then 1→ T, else 0 → TDeceq Dn 142 Deceqa Decrement and Set T If Equal Zero Deceqa Deceqa r0Rx 1 → Rx if Rx==0, then 1 → T, else 0 → T Deceqa Rx Deceqa Rx Decge Example decgeDn 1 → Dn Dn≥0 → T Decge Dn SC140 DSP Core Reference Manual 145 Decgea Decgea r4Rx 1 → Rx Rx ≥ 0 → T Decgea Rx Decgea Rx Determines execution working mode SR19 Set disable interrupt bit→ DI SR18Page DIV Divide Iteration DaluIf Dn39 ⊕ Da39 = Then 2 * Dn + C + Da & $FF Ffff 0000 → Dn Div d2,d1 DIV Da,Dn Dmacss Dmacss d2,d3,d5Dn16 + Dc.H * Dd.H → Dn Dc signed, Dd signed Dmacss Dc,Dd,Dn 1 1 Dmacsu Multiply Signed By Unsigned and Dmacsu Accumulate With Right Shifted Data Register DaluDmacsu d2,d3,d5 156 Do Enable Long Loop AGU Doen2 d0DOENn #u6 DOENn #u16 Loop Identifier #u6 Do Enable Short Loop AGU DOENSHn Doensh2 d0DOENSHn #u6 DOENSHn #u16 $00E4 $A0E4 Setup Long Loop DOSETUPn Dosetup1 labelPC + displacement → SAn DOSETUPn label Encoding is the displacement with SR19 Clears disable interrupt bit → DI 164 EOR Bitwise Exclusive or DaluEor d4,d5 Da ⊕ Dn → Dn EOR Da,Dn Eor #$5,d5.l EOR #u16,DR.LEOR #u16,DR.H EOR #u16,DR.L EOR #u16,DR.H EOR.W Bitwise Exclusive or on Eor.w #$aaaa,r0 Extract Extract Extract Signed Bit Field DaluExtract #$c,#$e,d2,d4 Extract #U6,#u6,Db,Dn Jjj Single Source/Destination Data Register Extractu Extractu Extract Unsigned Bit FieldExtractu #$c,#$e,d2,d4 Extractu #U6,#u6,Db,Dn Extractu #U6,#u6,Da,Dn Iaddnc.w #$a002,d2 IADDNC.W #s16,Dn Conditionally Execute a Group or Subgroup Prefix IFc If T == Then execute group/subgroupElse treat as NOP If T == Then execute group/subgroup Else treat as NOP Execute group/subgroup unconditionally Ift move.w #$ffff,d0 Ccc Conditional execution of the entire execution set Illegal Illegal Imac Imac d4,d5,d6Dn ± Da.L * Db.L → Dn Imac ±Da,Db,Dn Imac -d4,d5,d6 Accumulation Notation 182 Dn + Da.L * Db.H → Dn Imaclhuu Da,Db,Dn Imaclhuu Da,Db,Dn Imacus Integer Multiply AccumulateUnsigned By Signed Dalu Operation Assembler Syntax Imacus d3,d4,d0 $0002 x -64 $FFC0 -128 $FF80 +0 $0000 -128 $FF80 Impy Integer Multiply DaluDa.L * Db.L → Dn Impy Da,Db,Dn D1,D1 D3,D3 D5,D5 D7,D7 Impy.w #$fffe,d3 #s16 * Dn.L → DnIMPY.W #s16,Dn +16 Impyhluu Integer Multiply Upper ImpyhluuImpyhluu d4,d3,d0 Da.H * Db.L → Dn Impyhluu Da,Db,Dn Impysu Impysu d3,d5,d1Impysu Da,Db,Dn Register Bit Name Description Address Impysu Da,Db,Dn Impyuu Impyuu d5,d3,d1Impyuu Da,Db,Dn 196 INC INC Increment a Data Register By One Dalu OperationInc d0 INC Dn Inc d15 Inc.f d15 Dn + $0000010000 → DnINC.F Dn INC.F Dn Inca Increment Register AGUInca r0 Rx + 1 → Rx Inca Rx Insert Insert Bit Field DaluInsert #12,#22,d6,d7 Insert #U6,#u6,Db,Dn Insert #U6,#u6,Db,Dn Jump If False AGU JF lblJF label JF Rn Bit absolute long address JFD JFD labelJFD Rn $00E0 $00 0000 $0000 $00 0000 002A $00 0000 001A JMP Jump AGUJmp label JMP label JMP label Jump Using a Delay Slot AGU JmpdExample jmpd lbl Jmpd label AaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAAA JSR Jump to Subroutine AGUJsr r6 JSR label Absolute long address Example jsrd r6 Next* PC → RAS Rn → PCJsrd label Jsrd Rn Jsrd label Jump If True AGU Jt r0JT label JT Rn JT label Jump If True Using Delay Slot AGU JTDExample jtd r0 JTD label JTD label LPMARKx End-of-Loop Mark Prefix LPMARKx Operation If LCn Then SAn → PCLCn 1 → LCn Else next PC → PC → LFn If LCn Then SAn → PC LCn 1 → LCn Else next PC → PC → LFn → SLF Status and Conditions that Affect Lpmark Execution Table A-17. Combinations of LPMARKx UseLFn LCn Description Status and Conditions Changed by Lpmark Execution Prefix Formats and OpcodesInsertion of lpmarkb by assembler Instruction Disassembled Instruction Comments Lsll Multiple-Bit Bitwise Shift Left DaluLsll d4,d2 Lsll Da,Dn $00E4 $0$FF 8765 LSR Bitwise Shift Right One Bit DaluLsr d4 Dn1 → Dn 0 → Dn39 Lsra Bitwise Shift Right By One Bit AGULsra r2 Rx1 → Rx 0 → Rx31 Lsrr Multiple-Bit Bitwise Shift Right DaluLsrr Da,Dn Lsrr #u5,Dn Lsrr d4,d2 Before After Bit unsigned immediate data Lsrw Word Bitwise Shift Right DaluLsrw d4,d2 Lsrw Da,Dn Lsrw Da,Dn MAC Signed Fractional Multiply-Accumulate DaluMac d4,d5,d6 MAC #s16,Da,Dn Mac #$1000,d5,d6 SC140 DSP Core Reference Manual 235 Macr Macr d4,d5,d6RndDn ± Da.H * Db.H → Dn Macr ±Da,Db,Dn 000 0000 0000 1000 $0008 Instruction Formats and Opcodes 238 Macsu Macsu d0,d1,d4Dn + Dc.H * Dd.L → Dn Macsu Dc,Dd,Dn 111 1111 1111 1111 $FFFF Instruction Formats and Opcodes Macus Dn + Dc.L * Dd.H → DnMacus Dc,Dd,Dn Macus Dc,Dd,Dn Macuu Fractional Multiply-AccumulateUnsigned By Unsigned Dalu Operation Assembler Syntax Macuu d2,d3,d1 Macuu Dc,Dd,Dn Mark Push the PC into the Trace Buffer AGU MarkPC → trace buffer MAX Transfer Maximum Signed Value DaluMax d0,d4 If Dg Dh, then Dg → Dh MAX2 Max2 d0,d4If Dg.H Dh.H, then Dg.H → Dh.H If Dg.L Dh.L, then Dg.L → Dh.L 00 D0,D4 01 D1,D5 10 D2,D6 11 D3,D7 248 MAX2VIT If Da.L Db.L, then 0 → VFn, Da.L → Db.LElse 1 → VFn MAX2VIT Da,Db Max2vit d4,d2 Maxm Transfer Maximum Absolute Value Dalu Maxm Operation Maxm d2,d6Maxm Dg,Dh 00 D0,D4 01 D1,D5 10 D2,D6 11 D3,D7 252 MIN Transfer Minimum Signed Value DaluMin d1,d5 MIN Dg,Dh MOVE.2F Move Two Fractional Words from MOVE.2FMemory to a Register Pair AGU Description DaDb Data Register Pairs MOVE.2F EA,DaDb MOVE.2L Move.2l d0d1,r0Da,Db ↔ EA MOVE.2L DaDb,EA MOVE.2L EA,DaDb Read/Write Notation MOVE.2W Move.2w d0d1,r0EA ↔ DaDb MOVE.2W EA,DaDb MOVE.2W DaDb,EA $FF Ffff AF44 MOVE.4F Move Four Fractional Words from MOVE.4FMemory to a Register Quad AGU EA → DaDbDcDd Move.4f r0,d0d1d2d3 DaDbDcDd Data Register Quad MOVE.4W EA ↔ DaDbDcDdMOVE.4W EA,DaDbDcDd MOVE.4W DaDbDcDd,EA Move.4w d0d1d2d3,r0 MOVE.B Byte Move AGU Move.b d3,r7+$3 MOVE.B DR,eaMOVE.B SP+s15,DR MOVE.B DR,SP+s15 MOVE.B a16,DR A32 S15 MOVE.F Move Fractional WordTo/from Memory AGU Operation Assembler Syntax Move.f $54,d10 MOVE.F SP+s15,DbMOVE.F Db,ea MOVE.F #s16,Db MOVE.F a16,Db SC140 DSP Core Reference Manual 271 MOVE.L Move Long Word AGU Cccc General Registers #s32 #u32 MOVE.L SP+s15,De.E MOVE.L Da.EDb.E,SP+s15 Move.l d0.ed1.e,$1224 MOVE.L SP+s15,Do.EMOVE.L a32,De.E MOVE.L Da.EDb.E,a32 Data Register Da.EDb.E ff Data Register Extension Pair 278 Move Long AGU MOVE.L a32,DR MOVE.L DR,a32 MOVE.L a16,C4 MOVE.L C4,a16MOVE.L Rn+u3,DR MOVE.L DR,Rn+u3 MOVE.L Rn+s15,DR MOVE.L DR,Rn+s15 Move.l d0,r0 MOVE.L SP+s15,C4 MOVE.L C4,SP+s15 MOVE.L EA,DR MOVE.L DR,EA Rrr Address Register Read/Write Notation Unsigned 3-bit offset MOVE.W #s7,DR MOVE.W #s16,C4MOVE.W #s16,a16 MOVE.W #s16,SP-u5 Move.w #$0050,r7 MOVE.W #s7,DR MOVE.W #s16,C4 #s7 Sa16 MOVE.W Move Integer Word AGUMOVE.W a32,DR MOVE.W DR,a32 MOVE.W a16,C4 MOVE.W C4,a16 MOVE.W Rn+u3,DR MOVE.W DR,Rn+u3 MOVE.W Rn+s15,DR MOVE.W DR,Rn+s15MOVE.W Rn+Rr,DR MOVE.W DR,Rn+Rr MOVE.W Rn,C3 MOVE.W C3,Rn Move.w d1,r7+4 MOVE.W a32,DR MOVE.W DR,a32 Write Sss0 MOVEc Conditional Address Register Move AGU MOVEc Operation Movet r0,r1Movet Rq,Rn Movef Rq,Rn Qqq Address Register MOVES.2F Move Two Fractional Words to MOVES.2F DaDb → EAMOVES.2F DaDb,EA $7FFF $7EAC Moves.4f d0d1d2d3,r0 DaDbDcDd → EAMOVES.4F DaDbDcDd,EA $7FFF MOVES.F Move Fractional Word to Moves.f d0,r0 MOVES.F Db,a16 304 MOVES.L Move Long toMemory With Scaling and Saturation AGU Operation Moves.l d0,r0 MOVES.L Db,EA MOVEU.B Move Unsigned Byte fromMemory AGU Operation Assembler Syntax Moveu.b $0053,d10 MOVEU.B a16,DR 310 MOVEU.L Moveu.l #$fffffff8,d3#u32 → Db MOVEU.L #u32,Db 31IIIIIIIIIIIIIIII16 Moveu.w #$2345,d10.l #u16 → Db3116#u16 → Db150 MOVEU.W #u16,Db.H #u16 Iiiiiiiiiiiiiiii Bit unsigned immediate data MOVEU.W Move Unsigned Word fromMemory to a Register AGU Operation Moveu.w r7+2,d10 MOVEU.W a16,C4 318 MPY Mpy d4,d5,d6Da.H * Db.H → Dn MPY Da,Db,Dn Mpy d6,d6,d7 SC140 DSP Core Reference Manual 321 Mpyr Mpyr d4,d5,d6RndDa.H * Db.H → Dn Mpyr Da,Db,Dn $0000 Register/Memory Address Before After L6D6 324 Mpysu Mpysu d4,d5,d6Dc.H * Dd.L → Dn Mpysu Dc,Dd,Dn 326 Mpyus Dc.L * Dd.H → DnMpyus Dc,Dd,Dn 328 Mpyuu Mpyuu d4,d5,d6Dc.L * Dd.L → Dn Mpyuu Dc,Dd,Dn 330 NEG Negate DaluNeg d3 NEG Dn NEG Dn NOP No Operation PrefixNo operation Nop Not Bitwise Complement DaluNot d4,d5 ~Da → Dn SC140 DSP Core Reference Manual 335 Binary Inversion of a 16-Bit Operand BMU Not D0.L~DR.L → DR.L Not DR.L NOT.W Binary Inversion of a 16-Bit OperandMemory BMU Operation Assembler Syntax Not.w r1 Bitwise Inclusive or Dalu Example or d3,d0Da Dn → Dn Or Da,Dn SC140 DSP Core Reference Manual 341 Or #$0f0a,d0.l #u16 DR.L → DR.L#u16 DR.H → DR.H Or #u16,DR.L Or #u16,DR.L Or #u16,DR.H OR.W #u16,Rn OR.W #u16,SP-u5OR.W #u16,SP+s16 OR.W #u16,a16 Or.w #$f01a,r1 OR.W #u16,Rn 346 SP 8 → De SP 8 → SP SP 4 → Do SP 8 → SPPOP De POP Do Pop d3 Eeeee Extension Pairs, Even Registers, and Loop Start Registers NSP 8 → De NSP 8 → ΝSP NSP 4 → Do NSP 8 → ΝSP Popn d6.ed7.e Popn DePopn Do 352 De → SP SP + 8 → SP Do → SP + 4 SP + 8 → SPPush De Push Do Push d0.ed1.e SC140 DSP Core Reference Manual 355 De → NSP NSP + 8 → ΝSP Do → NSP + 4 NSP + 8 → ΝSPPushn De Pushn Do Pushn d0.ed1.e Pushn De Pushn Do RND Round DaluRndDa → Dn RND Da,Dn Rnd d1,d5 Rnd d2,d1 RND Da,Dn Rol d5 Dn3801 → Dn391Dn39 → C → Dn0 ROL Dn ROL Dn Ror d15 Dn39-11 → Dn38-0→ Dn39 Dn0 → C ROR Dn ROR Dn RTE SP 8 → PCSP 4 → SR SP 8 → SP → Nmid Rte Instruction Words Cycles1 Type Rted Example rted Trap RTS Return From Subroutine AGURts If RAS valid, then RAS → PC RTS Rtsd Rtsd Rtsd Restore PC from Stack AGU RtstkCleared Register Address Bit Name Description EMR3 Example rtstk Rtstkd SP 8 → PCSP 8 → SP Example rtstkd SAT.F Sat.f d2,d3If Da $007FFFFFFF then $007FFF0000 → Dn SAT.F Da,Dn SAT.F Da,Dn SAT.L Sat.l d6SAT.L Dn SC140 DSP Core Reference Manual 381 SBC Subtract With Borrow DaluDb Dc C → Dd SBC Dc,Dd SBC Dc,Dd SBR Subtract And Round DaluSbr d3,d0 RndDn Da → Dn 0010 1010 1110 0111 0000 0000 1000$2AE7 If LCn ≤ Then PC + displacement → PC Skipls label → LFn SkiplsSkipls label Skipls label Skipls label Stop Stop Stop Instruction Processing AGU OperationEnter the stop processing state SUB Subtract DaluSub d1,d0,d2 SUB #u5,Dn Sub d0,d1,d2 SC140 DSP Core Reference Manual 391 SUB2 Subtract Two 16-Bit Values DaluSub2 d0,d1 SUB2 Da,Dn Suba Subtract AGUSuba r1,r0 Suba #u5,Rx Suba Subl Shift Left and Subtract DaluSubl d0,d1 Dn Da → Dn $0$FF Ffff Fffe SUBNC.W Subnc.w #$15,d0Dn #s16 → Dn SUBNC.W #s16,Dn SUBNC.W #s16,Dn Sign-Extension Dalu Sxt.b d3,d0Sxt.w d3,d2 Sxt.l d3 Sign-Extension AGU Sxta.b r3,r1Sxta.w r3 SXTA.B TFR Transfer Data Register to Data Register DaluTfr d15,d14 Tfr d7,d6 TFR Da,Dn Tfra Tfra r0,r1Rx → Rx Tfra rx,Rx SC140 DSP Core Reference Manual 407 To/from a Register AGU If Srexp = Then NSP → RnElse ESP → Rn If Srexp = Then Rn → NSP Else Rn → ESP Tfra r0,osp Tfrt d14,d15 If T=1, then Da → DnIf T=0, then Da → Dn Tfrt Da, Dn Tfrt Trap Execute a Software Exception AGU Trap Operation TRAPn Trap Tsteq Test for Equal to Zero DaluTsteq d1 If Dn == 0, then 1 → T, else 0 → T TSTEQA.x Test for Equal to Zero AGU TSTEQA.x Operation Tsteqa.w r4Tsteqa.l r1 TSTEQA.W Rx TSTEQA.W TSTEQA.L Tstge Test for Greater Than Or Equal to Zero DaluTstge d4 If Dn = 0, then 1 → T, else 0 → T Tstgea.l r7 If Rx ≥ 0, then 1 → T, else 0 → TTESTGEA.L Rx TSTGEA.L Rx Tstgt Test for Greater Than Zero Dalu Tstgt Operation Tstgt d6If Dn 0, then 1 → T, else 0 → Τ Tstgt Dn Tstgta Test for Greater Than Zero AGU Tstgta Operation Tstgta r2If Rx 0, then 1 → T, else 0 → Τ Tstgta Rx Word Big Endian Mode Little Endian ModeVSL Viterbi Shift Left Move AGU VSL.4W D2D6D1D3,Rn+N0 VSL.4F D2D6D1D3,Rn+N0VSL.2W D1D3,Rn+N0 VSL.2F D1D3,Rn+N0 Vsl.2w d1d3,r0+n0 After Little EndianAfter Big Endian VSL.4W Enters the low-power standby Wait processing WaitState Response Wait Zero Extension Dalu Zxt.b d2,d5Zxt.w d3,d6 Zxt.l d0 Zero Extension AGU Zxta.b r3,n2Zxta.w r4 ZXTA.B ZXTA.x 432 Using the StarCore Registry Appendix B StarCore Registry Table B-1. Scid Assignments Hex Bits Instruction Cores ExampleSet Version SoC / platform Index Ecnten Eeddef Eselctrl 4-26ESELDI 4-26ESELDM 4-26ESELDTB 4-26 Eseletb MOVES.F A-299 MOVES.L A-301 MOVEU.B A-307 Macsu A-239 Macus A-241 Macuu A-243 Mpysu A-325 Mpyus A-327 Mpyuu A-329 Rtstk A-374 Index Index SC140 DSP Core Reference Manual

ADDL2A Add With Two-Bit Arithmetic Shift Left ADDL2A

of Source Operand (AGU)

Operation

(rx<<2) + Rx → Rx

ADDL2A rx,Rx

Status and Conditions that Affect Instruction

Description

EXP

AM3–AM0

Status and Conditions Changed by Instruction

Example

addl2a r0,r1

Register/Memory Address

In binary:

SC140 DSP Core Reference Manual