Freescale Semiconductor SC140 specifications Addressing Modes Summary, Memory Address Alignment

Address Generation Unit

Table 2-19 summarizes the memory address alignment rule for each type of memory access.

Table 2-19. Memory Address Alignment

Access Type	Aligned Address
Byte access	Any address
Word access	Multiple of 2
Long-word access	Multiple of 4
Two long-word access	Multiple of 8

2.3.3.7 Addressing Modes Summary

Table 2-20 provides a summary of the addressing modes described in the previous sections. The Operand Reference columns are abbreviated as follows:

•S = Software Stack Reference in data memory (uses NSP or ESP according to mode)

•C = Program Control Unit Register Reference

•D = DALU Register Reference

•A = AGU Register Reference

•P = Program Memory Reference

•X = Data Memory Reference

Table 2-20. Addressing Modes Summary

	R0-R7	Operand Reference
Addressing Modes	Uses							Assembler Syntax
	MCTL	S	C	D	A	P	X
	Register Direct
Data or Control Register	—		√	√				Dn
								Dn Dm
								Dn Dm Di Dj
								MCTL
								SR, EMR, VBA
								LC0, LC1
								LC2, LC3
								SA0, SA1
								SA2, SA3
Address Register (Rn)	—				√			Rn
Address Modifier Register (Mj)	—				√			Mj
Base Address Register (Bn)	—				√			Bn
Address Offset Register (Ni)	—				√			Ni
Stack Pointer	—				√			SP

SC140 DSP Core Reference Manual 2-43