Freescale Semiconductor SC140 specifications Example 5-4. Conditional Vles Having Two Subgroups

Instruction Grouping

Example 5-3. Execution Set with Three One-word and Two Two-word Instructions

Position	0	1	2	3	4	5	6	7
	1w prefix	2w	- - ext	1w	2w - - ext		1w	1w

The instruction reordering by the assembler operates as follows:

•Instruction words of an execution set must be encoded contiguously. No encoding gaps are allowed.

•Up to two AGU instructions may appear in an execution set. One must encode in an even position. The other must encode in an odd position. If there is only one AGU instruction, it can be encoded anywhere.

•Up to four DALU instructions may appear in an execution set. These DALU instructions must encode in different positions in modulo 4 arithmetic. For example, two DALU instructions in the same set cannot be encoded in positions 0 and 4, positions 1 and 5, and so on.

•An execution set with a prefix can contain up to 2 two-word instructions. One two-word instruction must encode in an even position and the other in an odd position. Thus, the 2 two-word instructions of an execution set must be encoded with an odd number of instruction words between them.

•Some execution sets contain two conditional subgroups using IFT/IFF/IFA instructions:

Example 5-4. Conditional VLES Having Two Subgroups

IFT ADD D0,D1,D2 RND D2,D3 IFF SUB D0,D1,D2 ADDA R0,R1

Instructions within a conditional VLES are assigned to two subgroups as follows:

—Subgroup1 — Instructions encode in the even word positions.

—Subgroup2 — Instructions encode in the odd word positions.

This means that in any subgroup one cannot have more then one two-word instruction. (since according to the previous bullet one two-word instruction should be in even place and the other in odd).

In this example, instructions of the IFT subgroup encode in subgroup1 (even word positions) while instructions of the IFF subgroup encode in subgroup2 (odd word positions) of the VLES. The assembly syntax completely hides this interleaved encoding from the programmer.

•In cases where more than one DALU instruction in the execution set affects the carry bit C in SR (according to the instruction definition), the last (right or bottom in the assembly source code) carry-updating instruction that actually executes updates the carry bit while the other instructions do not affect the carry bit. If no carry-affecting instructions execute, the carry bit is not affected. The assembler keeps the last carry-affecting instruction as the last (highest position) carry-affecting instruction in the VLES encoding. For two IFc subgroups, this encoding rule applies independently to each subgroup encoding.

In some cases, the assembler adds a NOP instruction during the encoding process. For example, if 2 two-word instructions are grouped, they must be separated by an odd number of instruction words. If no one-word instructions are included in the set, the assembler inserts a NOP instruction. Example 5-5 illustrates such a case.

Example 5-5. Set of 2 Two-word Instructions Requiring a NOP

MOVE #xxxx,D0 MOVE #xxxx,D1

SC140 DSP Core Reference Manual 5-13