Freescale Semiconductor SC140 specifications Core-PIC Interface

Exception Processing

Figure 5-11 below depicts the core interface to an external interrupt controller.

INTERRUPT OFFSET	6		6
NMI_REQ			20
IREQ
			VBA
AUTO_VEC		6
3			PAB
IPL		Program
			Internal
		Sequencer
			Exceptions
		PSEQ
			SC140

Figure 5-11. Core-PIC Interface

The interface signals (inputs to the core from an external interrupt controller) are described in the following list.

•Maskable Interrupt Request Signal (IREQ) — Asserted to inform the core of a pending maskable interrupt request.

•Interrupt Request Priority Level (IPL) — This 3-bit bus defines the priority level of the maskable interrupt request. If this value exceeds the value encoded in the SR bits I[2:0], the interrupt can be serviced. Otherwise, it is masked.

•Non-maskable Interrupt Request (NMI_REQ) — Assertion of this signal initiates an interrupt independent of the value on the IPL bus or the SR priority level. This input can be inhibited by the non-masked interrupt disable (NMID) bit in the Exception and Mode Register (EMR).

•Enable Auto-vector (AUTO_VEC) — This signal selects the source for the offset part of the interrupt vector address: either the default offset or the value driven by the user on the 8-bit INTERRUPT OFFSET bus. This selection affects both maskable and non-maskable interrupts.

•INTERRUPT OFFSET — This 6-bit value can be the offset address applied to the interrupt vector address table. It is selected if the AUTO_VEC (above) does not select the default offset. The complete address of the interrupt vector is defined by a number of fields. For more details, see Section 5.8.1.2, “Programming Exception Routine Addresses.”

The following list outlines how exceptions are processed by the SC140:

1.The hardware interrupt request is synchronized with the core clock. The interrupt pending request signal for that particular hardware interrupt is set. An internal exception (such as an illegal instruction) is processed in the PSEQ internally as a non-maskable exception request. An exception source can have only one exception pending at any given time.

2.The PSEQ in the core automatically ignores any interrupt request with an IPL lower than or equal to the interrupt mask level in the SR. NMIs and internal exceptions are serviced regardless of the current IPL.

SC140 DSP Core Reference Manual 5-47