Freescale Semiconductor SC140 specifications Debug State, Wait Processing State

Processing States

5.7.5 Debug State

The debug state is a special core processing state in which the pipeline is stalled and waits for user commands from the JTAG or EOnCE. The core can enter the Debug state in the following cases:

•JTAG issues a debug request is asserted, in all states.

•The EE0 EOnCE signal is asserted during reset.

•The EE0 EOnCE signal is asserted anytime, if programmed as a debug request input in the EE_CTRL register.

•An EOnCE Debug state event occurs.

•A DEBUG instruction is executed, if the SDD in EMR is not set, and the EOnCE is programmed so that it will generate a Debug state event.

•A DEBUGEV instruction is executed, and the EOnCE is programmed so that it will generate a Debug state event.

If EE0 or the JTAG debug request are asserted during reset and continue to be asserted when reset is de-asserted, the core enters the debug state without executing any instruction.

The debug state is exited by setting the exit bit in the EOnCE command register by JTAG. Refer to Chapter 4, “Emulation and Debug (EOnCE),” for a detailed description of the user commands in the debug state.

5.7.6 Wait Processing State

The wait processing state is a low-power consumption state entered by the execution of the WAIT instruction. After a system-specific delay of some cycles from the issue of the WAIT instruction, the core’s global clock is turned off. Peripherals can continue to operate, but all internal processing is halted until one of the following actions occurs:

•An interrupt, with enabled priority, is issued1.

•A non-maskable interrupt (NMI) request is issued.

•A low-level is applied to the RESET signal (RESET asserted).

•The JTAG issues a debug request.

•The EOnCE EE0 signal (programmed as a debug request input) is asserted.

Debug request from the EOnCE may also exit from Wait Processing State, if it occur a few cycles after the WAIT instruction execution (exact time may vary according to the specific clock scheme implemented).

If an exit from the Wait Processing State is caused by assertion of the EE0 signal or a debug request, the core either enters the debug state immediately, or the debug exception is serviced according to the EOnCE configuration. Refer to Chapter 4, “Emulation and Debug (EOnCE),” , for further details.

If the Wait Processing State is exited by assertion of the RESET signal, the core enters the reset processing state.

Table 5-18 describes exit from Wait Process State, due to interrupt and NMI, under various core conditions.

1. i.e. IPL of the interrupt is greater than the core IPL, as determined by bits I2-I0 of the SR. See Table 5-18 for more information.

5-44 SC140 DSP Core Reference Manual