Freescale Semiconductor SC140 Exception Interface to the Pipeline, Dalu Overflow, Trap Exception

Exception Processing

instruction also occurred during this period, the ILIN bit in EMR will be set to indicate multiple causes for this illegal exception. If the illegal exception service routine has an illegal execution set, nested illegal exceptions will occur.

5.8.5.2 DALU Overflow

The DALU overflow exception is generated whenever an overflow occurs as a result of a DALU operation. Whenever there is an overflow, an exception is generated and the DOVF bit in the EMR is set, if the exception enable bit OVE in the SR is set. The DOVF bit blocks subsequent DALU overflow exceptions. Once the DOVF bit is set, no additional DALU overflow exceptions will occur until the DOVF bit is cleared. Although useful for algorithm debugging, the overflow exception routine may be unable to take corrective action due to the imprecise nature of this exception.

The PC of the execution set causing the overflow exception is saved in the PC_EXCP register of the EOncE.

5.8.5.3 TRAP Exception

Immediately after executing a TRAP instruction, the core enters the exception mode. Both the PC and SR values are pushed onto the exception stack. The IPL is set to its maximum value and the exception mode is entered. This exception is precise. It occurs immediately after the execution set that contains the TRAP instruction.

The TRAP instructionis typically used for RTOS calls.

5.8.5.4 Debug Exception

A debug exception can be initiated as a result of a debug event, as configured in the EOnCE. It is also possible to configure the DEBUG and DEBUGEV instructions to generate a debug exception. This exception is not precise. Please refer to Chapter 4, “Emulation and Debug (EOnCE),” for further details.

5.8.6 Exception Interface to the Pipeline

When an interrupt request signal is asserted or an internal exception is triggered, the PSEQ finds the first possible time slot to interrupt the current program flow and start servicing the exception. The PSEQ will delay an exception service when the current pipeline state cannot be interrupted safely without damaging the running task. In most cases, only one cycle is consumed for the exception servicing (for pushing the return address and the SR onto the exception software stack). From this point on, the exception handling routine is treated like any normal flow code. The sections that follow describe the exception process.

5.8.6.1 Exception Routine Fetch

When the PSEQ acknowledges an exception request for service, the exception vector address is driven onto the program address bus. The core then enters exception mode, fetching instructions starting at the exception vector address.

5-52 SC140 DSP Core Reference Manual