Core Architecture Features
SC140 DSP Core Reference Manual 1-3
1.3 Core Architecture Features
The SC140 core consists of the following:
•Data arithmetic logic unit (DALU) that contains four instances of an arithmetic logic unit (ALU) and
a data register file
•Address generation unit (AGU) that contains two address arithmetic units (AAU) and an address
register file
•Program sequencer and control unit (PSEQ)
Key features of the SC140 core include the following:
•Up to four million multiply-accumulate (MAC) operations per second (4 MMACS) for each
megahertz of clock freq uency
•Up to 10 RISC MIPS (million instruction words per second) for each megahertz of clock frequency
(a MAC operation is counted as two RISC instructions)
•Four ALUs comprising MAC and bit-field units
•A true (16 ∗ 16) + 40 to 40-bit MAC unit in each ALU
•A true 40-bit parallel barrel shifter in each ALU
•Sixteen 40-bit data registers for fractional and integer data operand storage
•Sixteen 32-bit address registers, eight of which can be used as 32-bit base address registers
•Four address offset registers and four modulo address registers
•Hardware support for fractional and integer data types
•Up to six instructions executed in a single clock cycle
•Very rich 16-bit wide orthogonal instruction set
•Support for application specific instruction set enhancements with an interface to an ISAP
(Instruction Set Accelerator Plug-in)
•VLES execution model
•Two AAUs with integer arithmetic capabilities
•A bit mask unit (BMU) for bit and bit-field logic operations
•Unique DSP addressing modes
•32-bit unified data and program address space
•Zero-overhead hardware loops with up to four levels of nesting
•Byte-addressable data memory
•Position independent code utilizing change-of-flow instructions that are relative to the
program counter (PC)
•Enhanced on-chip emulation (EOnCE) module with real-time debug capabilities
•Low power wait standby mode
•Very low power complementary metal-oxide semicondu ctor (CMOS) design
•Fully static logic