Freescale Semiconductor SC140 specifications Control Registers

Chapter 3

Control Registers

3.1	Core Control Registers	. 3-1
3.1.1	Status Register (SR)	. 3-1
3.1.2	Exception and Mode Register (EMR)	. 3-7
3.1.2.1	Clearing EMR Bits	3-10
3.2	PLL and Clock Registers	3-10
	Chapter 4
	Emulation and Debug (EOnCE)
4.1	Debugging System	. 4-1
4.2	Overview of the Combined JTAG and EOnCE Interface	. 4-2
4.2.1	Cascading Multiple SC140 EOnCE Modules in a SoC	. 4-2
4.2.2	JTAG Scan Paths	. 4-3
4.2.3	Activating the EOnCE Through the JTAG Port	. 4-6
4.2.4	Enabling the EOnCE Module	. 4-6
4.2.5	DEBUG_REQUEST and ENABLE_EONCE Commands	. 4-7
4.2.6	Reading/Writing EOnCE Registers Through JTAG	. 4-7
4.3	Main Capabilities of the EOnCE Module	4-10
4.3.1	EOnCE Signals	4-10
4.3.2	EOnCE Dedicated Instructions	4-11
4.3.3	Debug State	4-11
4.3.4	Debug Exception	4-12
4.3.5	Executing an Instruction while in Debug State	4-12
4.3.6	Software Downloading	4-12
4.3.7	EOnCE Events	4-14
4.3.8	EOnCE Actions	4-15
4.3.9	Event and Action Summary	4-15
4.4	EOnCE Enabling and Power Considerations	4-16
4.5	EOnCE Module Internal Architecture	4-16
4.5.1	EOnCE Controller	4-16
4.5.2	Event Counter	4-18
4.5.3	Event Detection Unit (EDU)	4-20
4.5.3.1	Address Event Detection Channel (EDCA)	4-22
4.5.3.2	Data Event Detection Channel (EDCD)	4-24
4.5.3.3	Optional External Event Detection Address Channels	4-25
4.5.4	Event Selector (ES)	4-25
4.5.5	Trace Unit	4-26
4.5.5.1	Change of Flow and Interrupt Tracing	4-28
4.5.5.2	Writing to the Trace Buffer	4-29
4.5.5.3	Reading the Trace Buffer (TB_BUFF)	4-29
4.5.5.4	Trace Unit Programming Model	4-29
4.6	EOnCE Register Addressing	4-30
4.6.1	Reading or Writing EOnCE Registers Using Core Software	4-33
4.6.2	Real-Time JTAG Access	4-33
4.6.3	Real-Time Data Transfer	4-34

SC140 DSP Core Reference Manual v