Freescale Semiconductor SC140 EOnCE Monitor and Control Register Emcr, describes the Emcr fields

EOnCE Controller Registers

4.7.3 EOnCE Monitor and Control Register (EMCR)

The EMCR is a 32-bit register. Bits 31–16 are read/write control bits. Bits 15–0 are sticky status bits and can only be written with zeros. Writing them with a one has no effect. The sticky status bits of the register indicate an event generated by the EOnCE EDU.

Figure 4-17 displays the configuration of EMCR.

BIT	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
31

PICINT TRSINT TBFDM RCVINT

DEBUGERST

SWDIS IME

TYPE	rw	rw	rw	rw	rw	rw	rw	rw	rw			rw		rw		rw		rw	rw	rw	rw
RESET	0	0	0	0	0	0	0	0	0			0		0		0		0	0	0	0
	BIT 15	14	13	12	11	10	9	8	7		6	5				4		3	2	1	BIT 0
	DIS							EDCD	EDCA	EDCA			EDCA		EDCA		EDCA		EDCA	EDCA	EDCA
								ST	ST7		ST6		ST5		ST4			ST3	ST2	ST1	ST0
TYPE	rw	rw	rw	rw	rw	rw	rw	rw	rw		rw		rw			rw		rw	rw	rw	rw
RESET	0	0	0	0	0	0	0	0	0		0	0				0		0	0	0	0

The shaded bits are reserved and should be initialized with zeros for future software compatibility.

Figure 4-17. EOnCE Monitor and Control Register (EMCR)

Table 4-15 describes the EMCR fields.

	Table 4-15. EMCR Description
Name	Description
R	Reserved
Bits 31–26
PICINT	PIC interrupt - When set, and there is a condition that would have caused a
Bit 25	debug exception, the EOnCE will assert an external pin to an external interrupt
	controller. When reset, the core generates an internal debug exception for the
	same event. This bit is for the use of the system engineer.
TRSINT	Transmit Interrupt — Can be set for interrupt driven data messaging. If this bit is
Bit 24	set and the TRSMT bit is reset by the EOnCE, a debug exception is issued. The
	core ISR determines the reason for the interrupt and writes the new data to the
	ETRSMT register.
TBFDM	Enter Debug on Trace Buffer Full — When TBFDM is cleared, the trace buffer
Bit 23	wraps around when full and does not affect core execution. After write pointer
	wrap-around, the trace buffer over-writes the oldest entries like a modulo buffer.
	When TBFDM is set, the trace buffer almost-full condition affects core execution
	according to the IME bit. For this condition, IME cleared causes the core to enter
	debug state and IME set causes the core to take the debug exception. TBFDM is
	cleared on RESET
RCVINT	Receive Interrupt — Can be set by the user for interrupt driven data messaging
Bit 22	from the host to the target. If this bit is set and the RCV bit is set by the EOnCE, a
	debug exception is issued. The core interrupt service routine (ISR) determines the
	reason for the interrupt and reads the content of the ERCV register.

SC140 DSP Core Reference Manual 4-41