I-6 Index
NOT.W A-338
OR A-340, A-342
OR.W A-344
POP A-347
POPN A-350
PUSH A-353
PUSHN A-356
RND A-359
ROL A-362
ROR A-364
RTE A-366
RTED A-368
RTS A-370
RTSD A-372
RTSTK A-374
RTSTKD A-376
SAT.F A-378
SAT.L A-380
SBC A-382
SBR A-384
SKIPLS A-386
STOP A-388
SUB A-389
SUB2 A-392
SUBA A-394
SUBL A-396
SUBNC.W A-398
SXT.x A-400
SXTA.x A-402
TFR A-404
TFRA A-406, A-408
TFRc A-410
TRAP A-412
TSTEQ A-414
TSTEQA.x A-415
TSTGE A-417
TSTGEA.L A-418
TSTGT A-420
TSTGTA A-421
VSL A-422
WAIT A-426
ZXT.x A-428
ZXTA.x A-430
Instruction set accelerator 2-5
Instruction Set Accelerator Plug-In 6-57
IPL (interrupt priority level) 3-3
ISAP 2-5, 6-57
allocating encoding space 6-60
Conditional execution 6-66
How the core identifies ISAP instructions 6-63
Programming rules 6-67
working with a single ISAP 6-58
working with data and memory 6-60
Working with multiple ISAPs 6-59
J
JF A-205
JFD A-207
JMP A-209
JMPD A-211
JSR A-213
JSRD A-215
JT A-217
JTAG 5-44, 5-45
JTAG access 4-33
JTAG and EOnCE interface 4-2
JTAG interface pins 4-2
JTD A-219
L
LF3-0 (loop flags 3-0) 3-2
Linear addressing mode 2-45
Loop
looping rules 5-32
nested loop 5-31
timing 5-32
LPMARKx 5-26, A-221
LSLL A-224
LSR A-226
LSRA A-227
LSRR A-228
LSRW A-231
M
M0-M3 (modifier registers) 2-36
MAC A-233
MAC (multiply-accumulate) 1-3, 2-3, 2-10
MAC unit
arithmetic instructions 2-10
MACR A-236
MACSU A-239
MACUS A-241
MACUU A-243
MARK A-245
MAX A-246
MAX2 A-247
MAX2VIT A-249
MAXM A-251
MCTL (mod ifier control register) 2-37
MCTL register
AM bits 2-37
Memory
on-chip 2-5
Memory access
behavior in big/little endian modes 2-64
memory access misalignment 2-42
Memory interface 2-55
Memory organization 2-57