Freescale Semiconductor SC140 General Grouping Rules, Rule G.G.1, Rule G.G.2, Rule G.G.3

Static Programming Rules

•The SAn register contains the starting address of the first VLES of long loop n.

These assumptions ensure the LOOPSTARTn and LOOPENDn directives are consistent with the hardware loop state machine’s decoding of the LPMARKx bits. The assembler may not detect hardware loop rules if these assumptions are violated.

7.5.2 General Grouping Rules

Rule G.G.1

Up to 6 instructions can be grouped in a VLES. Prefix instructions (IFc, LPMARKx, and NOP) are not counted for this rule.

Rule G.G.2

Up to eight instruction words (including prefix words) can be grouped in a VLES.

Example 7-3. VLES Word Count Exceeds Eight

jmpd r5 adr d0,d12 adr d1,d2 adr d2,d3 adr d5,d6 move.l #$12345678,r0

This example is not allowed. There are six instruction words plus two MOVE extension words and two prefix words.

Rule G.G.3

Instructions grouped in a VLES cannot exceed the available execution units. The maximum number of instructions in a VLES is:

•DALU instructions listed in Table A-7: DALU Arithmetic Instructions (MAC) on page A-13 and

Table A-8: DALU Logical Instructions (BFU) on page A-14.

•Two AGU instructions, including:

—All AGU arithmetic instructions listed in Table A-9: AGU Arithmetic Instructions on page A-15.

—All AGU move instructions listed in Table A-10: AGU Move Instructions on page A-16.

—All AGU stack support instructions listed in Table A-11: AGU Stack Support Instructions on page A-16

—All control instructions listed in Table A-13: AGU Non-LoopChange-of-Flow Instructions on

page A-17,Table A-14: AGU Loop Control (Including Loop COF) Instructions on page A-18,

and Table A-15: AGU Program Control Instructions on page A-18.

•One bit-mask (BMU) instruction listed in Table A-12: AGU Bit-Mask Instructions (BMU) on page A-17. This instruction is also counted as an AGU instruction.

•One ISAP opcode (2-w prefix encoding) per VLES. An ISAP can be defined to support more than one instruction per ISAP opcode, Section 6.3, “ISAP instructions and instruction encoding.”

•This rule does not apply to prefix instructions listed in Table A-16: Prefix Instructions on page A-18 because they do not allocate execution units.

Example 7-4 Too Many AGU Instructions

bmtsts #$eb22,d5.h move.w r2,(r0)+ move.w r2,(r5) ;not allowed

7-8 SC140 DSP Core Reference Manual