2-2 SC140 DSP Core Reference Manual
Architecture Overview
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Figure 2-1. Block Diagram of the SC140 Core
2.1.1 Data Arithmetic Logic Unit (DALU)
The DALU performs arithmetic and logical operations on data operands in the SC140 core. The
components of the DALU are as follows:
•A register file of sixteen 40-bit registers
•Four parallel ALUs, each ALU containing a multiply-accumulate (MAC) unit and
a bit-field unit (BFU)
•Eight data bus shifter/limiters
All the MAC units and BFUs can access all the DALU registers. Each register is partitioned into three
portions: two 16-bit registers (low and high portion of the register) and one 8-bit register (extension
portion). Accesses to or from these registers can be in widths of 8 bits, 16 bits, 32 bits, or 40 bits,
depending on the instruction.
The two data buses between the DALU register file and the memory are each 64 bits wi de. This enables a
very high data transfer speed between memory and registers by allowing two data moves in parallel, each
up to 64 bits in width. The move instructions vary in access width from 8 bits to 64 bits, and can transfer
multiple words within the 64 bit constraint. With every MOVE instruction affecting the memory, one of
four signals to the memory interface is asserted, defining the access width.
•MOVE.B loads or stores bytes (8-bit).
•MOVE.W or MOVE.F loads or stores integer or fractional words (16-bit).
•MOVE.2W, MOVE.2F or MOVE.L loads or stores two integers, two fractions and long words
respectively (32-bit).
•MOVE.4W or MOVE.4F loads or stores four integers or four fractions, respectively (64-bit).
XDBA
XABA
Instruction Bus
PAB
Program
Sequencer
PDB
XABB
XDBB
DALU
Register File
Unified
64
64
32
32
32
128
BMU
25
Data/Program Memory
StarCore
SC140
Core
Address Generator
Register File
DALU
AGU
ISAP
EOnCE
JTAG
controller
2 AAUs 4 ALUs