Freescale Semiconductor Isap SC140 Schematic Connection, Single Isap, Data Memory, SC140Core

ISAP - SC140 Schematic Connection

6.2 ISAP - SC140 Schematic Connection

The ISAP-SC140 connection actually involves an external data memory bank as well. Two connection schemes are shown: SC140 to single ISAP, and SC140 to multiple ISAPs.

6.2.1 Single ISAP

Connection with the ISAP is illustrated in Figure 6-1 below:

Data Memory

B)

dA rd se bs esu (s ,A

2 Read buses (A,B) 2 2 Write buses (A, B)

SC140Core	ISAP - Core	ISAP
	Register channel

Core to ISAP instruction dispatch

Figure 6-1. Core to Single ISAP Connection Schematic

The ISAP receives instructions from the core via a dedicated ISAP instruction dispatch bus, up to once per execution set.

The ISAP is connected to the data memory via the same two data buses XDBA and XDBB as the core, in both read and write directions. The SC140 core is the only address generating master of the data buses. The ISAP does not send address information to the Data memory, hence the ISAP does not need an AGU. A data access to or from the ISAP requires a parallel core AGU MOVE instruction that generates the access on the address and control lines to the memory. The ISAP then drives or samples the data buses accordingly. The way the ISAP memory access is shared between the core and the ISAP is described in Section 6.4, “ISAP Memory Access.” .

6-58 SC140 DSP Core Reference Manual