Freescale Semiconductor SC140 specifications Program Control

Chapter 5

Program Control

5.1	Pipeline	. 5-1
5.1.1	Instruction Pipeline Stages	. 5-2
5.1.1.1	Instruction Pre-Fetch and Fetch	. 5-4
5.1.1.2	Instruction Dispatch	. 5-4
5.1.1.3	Address Generation	. 5-4
5.1.1.4	Execution	. 5-5
5.2	Instruction Grouping	. 5-5
5.2.1	Grouping Types	. 5-6
5.2.1.1	Serial Grouping	. 5-7
5.2.1.2	Prefix Grouping	. 5-7
5.2.2	Prefix Types	. 5-8
5.2.2.1	Two-Word Prefix	. 5-8
5.2.2.2	One-Word Low Register Prefix	. 5-9
5.2.3	Conditional Execution	. 5-9
5.2.4	Prefix Selection Algorithm	5-10
5.2.5	Instruction Reordering Within an Execution Set	5-12
5.3	Instruction Timing	5-14
5.3.1	Sequential Instruction Timing	5-15
5.3.1.1	DALU Instruction Timing	5-16
5.3.1.2	Move Instruction Timing	5-16
5.3.1.3	Bit Mask Instruction Timing	5-16
5.3.2	Change-Of-Flow Instruction Timing	5-17
5.3.2.1	Direct, PC-Relative, and Conditional COF	5-18
5.3.2.2	Delayed COF	5-19
5.3.2.3	COF Execution Cycles	5-19
5.3.3	Memory Access Timing	5-21
5.3.3.1	Memory Access Examples	5-22
5.3.3.2	Implicit Push/Pop Memory Timing	5-24
5.3.3.3	Memory Stall Conditions	5-24
5.4	Hardware Loops	5-25
5.4.1	Loop Programming Model	5-25
5.4.1.1	Loop Start Address Registers (SAn)	5-25
5.4.1.2	Loop Counter Registers (LCn)	5-26
5.4.1.3	Status Register (SR) Loop Flag Bits	5-26
5.4.2	Loop Notation and Encoding	5-26
5.4.3	Loop Initiation and Execution	5-27
5.4.4	Loop Nesting	5-28
5.4.5	Loop Iteration and Termination	5-28
5.4.6	Loop Control Instructions	5-29
5.4.7	Loop Timing	5-32
5.5	Stack Support	5-32
5.5.1	SC140 Single Stack Memory Use	5-32
5.5.2	SC140 Dual Stack Memory Use	5-33
5.5.3	Stack Support Instructions	5-34
5.5.4	Shadow Stack Pointer Registers	5-35

SC140 DSP Core Reference Manual vii