Freescale Semiconductor SC140 specifications Core Command Register Corecmd, Length Control Bits

EOnCE Controller Registers

4.7.7 Core Command Register (CORE_CMD)

The CORE_CMD register is used to execute instructions in the core while in debug state. The external host writes the instruction into the CORE_CMD register as described in Section 4.2.6, “Reading/Writing EOnCE Registers Through JTAG.” The EOnCE commands written into the ECR must be Write CORE_CMD and GO. After writing the instruction into the CORE_CMD register, the core executes it without leaving debug state. If the EX bit in ECR is also set, debug state is exited after the instruction is performed.

The format of the injected command is shown in Figure 4-19 below.

Bit 47 34 33 20 19 4 3 2 1 0

ImmB

14bits

bits [0:13]

ImmA

14bits

bits [0:13]

Opcode

16bits

bits [0:15]

Ext.

Prefix 2 bits

Length Control 2 bits

CORE_CMD

{Prefix1[5], Prefix1[7]}

	Prefix1	Prefix2	Opcode	ImmA	ImmB
Instruction Bus (IB)	[15:0]	[15:0]	[15:0]	[15:0]	[15:0]

Figure 4-19.Injected Instruction Format

The length control bits are described in Table 4-17, below:

Table 4-17. Length Control Bits

Length Control Bits		Description
0	0	Not supported

01 One word instruction

10 Two word instruction

1 1 Three word instruction

The two prefix bits allow the instruction to use the high bank of registers. Bits 15 and 14 in the second and third words encode the grouping/word partition used by the core for execution set parsing. In the case of a single instruction, they do not need to be part of the CORE_CMD word. For further details, see Appendix A, “SC140 DSP Core Instruction Set.”

In general, core commands should not perform illegal operations. In case a core command generated an exception (such as an illegal exception), the exception will be serviced only after the core exits debug state.

4-48 SC140 DSP Core Reference Manual