Freescale Semiconductor SC140 Move Four Fractional Words from MOVE.4F, EA → DaDbDcDd

MOVE.4F

MOVE.4F	Move Four Fractional Words from MOVE.4F
	Memory to a Register Quad (AGU)
Operation	Assembler Syntax
(EA) → Da:Db:Dc:Dd	MOVE.4F (EA),Da:Db:Dc:Dd {0 ≤ EA < 232,Q}

Description

MOVE.4F (EA),Da:Db:Dc:Dd

Reads four signed fractional words from memory to a data register quad (Da:Db:Dc:Dd). The effective memory address of the four words is contained in an address register with an optional offset or post-increment (EA). Each word is written into the HP of its respective data register, is sign-extended, and the LP is zero-filled. The reverse operation (moving from a register quad to memory) is done with saturation as described by MOVES.4F.

The first operand (Da) will be moved from the lower memory address (EA). The second operand (Db) will be moved from memory address (EA + 2). The third operand (Dc) will be moved from memory address (EA + 4). And, the fourth operand (Dd) will be moved from memory address (EA + 6). In order to keep this behavior in both big endian and little endian modes, the core will interpret the data bus differently in each mode. See Section 2.4.1, “SC140 Endian Support,” on page 2-56, for more detail on bus and memory behavior for each mode.

The address register values used with this instruction must be a multiple of 8, quad word-aligned

	39	32	16	0
Da		SIGN	(EA)	ZERO FILL
	EXTENSION
Db		SIGN	(EA + 2)	ZERO FILL
	EXTENSION
Dc		SIGN	(EA + 4)	ZERO FILL
	EXTENSION
Dd		SIGN	(EA + 6)	ZERO FILL
	EXTENSION

Status and Conditions that Affect Instruction

Register Address	Bit Name	Description
MCTL[31:0]	AM3–AM0	Address modification bits when updating R0–R7. Otherwise, the
		instruction is not affected by MCTL.
EMR[16]	BEM	Set if big endian mode, cleared if little endian mode.

Status and Conditions Changed by Instruction

Register Address	Bit Name	Description
Ln	L	Clears the Ln bit in the destination registers.

Example

A-260 SC140 DSP Core Reference Manual