Freescale Semiconductor SC140 describes the ESR fields, ESR Description, Name Description

EOnCE Controller Registers

BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0

DRSW DREE DREE DREE DREE DREE DRCOUN-

4 3 2 1 0 TER

DREDCD DRED DRED DRED DRED DRED DRED DRED DRED CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0

TYPE	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r
RESET	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

The shaded bits are reserved and should be initialized with zeros for future software compatibility. The reset values for REVNO and CORETP (shown as x) are derivative-dependent.

Figure 4-16. EOnCE Status Register (ESR)

Table 4-14 describes the ESR fields.

		Table 4-14. ESR Description
Name	Description
CORES	Core Status — Provides core status information. Indicates whether the core has
Bits 31-30	entered debug state and the reason. These bits are also reflected in the JTAG
	instruction shift register, which allows for the polling of core status information at
	the JTAG level. This is useful in case the core software executes a STOP
	instruction so there are no clocks for reading the core status. The settings for these
	bits are as follows:
	•	00 =	Core is executing instructions.
	•	01 =	Core is in wait or stop mode.
	•	10 =	Core is waiting for a bus.
	•	11 =	Core is in debug state.
	The “waiting for a bus” state indicates that the core is waiting for data on the bus to
	be transferred, or that the core is disabled by the external system (for example
	during memory BIST).
	The core could be waiting for a bus in any of the processing states. In such a case
	the CORES field will show “waiting for a bus”.
R	Reserved
Bit 29
PCKILL	PC Killed — This bit signifies that the last executed VLES was aborted by a
Bit 28	pending exception. It is set by the EOnCE when the last execution set has been
	aborted, and cleared when starting to perform the next single step. This bit is valid
	only in debug state, and is useful particularly while single stepping.
RCV	Receive — Set by the EOnCE when the host has finished writing to the ERCV
Bit 27	register. The bit is cleared by EOnCE when both halves of the ERCV register
	contents are read by the core. The two halves are read in a specific order with the
	LSB read first. The RCV bit is cleared when the MSB has been read without
	checking if the LSB part has been read.
TRSMT	Transmit — Set by the EOnCE when both halves of the ETSMT register are
Bit 26	written by the core. The two halves are written in a specific order with the LSB
	written first. The TRSMT bit is set when the MSB has been written without
	checking if the LSB part has been written. The bit is cleared by EOnCE when the
	host has finished reading the content of the ETRSMT register.

4-38 SC140 DSP Core Reference Manual