Freescale Semiconductor SC140 specifications Ecnten

CCS (comparator condition selection bits) 4-60Change-of-flow instructions 2-68

CLB A-113

CLR A-115 CMPEQ A-117CMPEQ.W A-119CMPEQA A-121CMPGT A-123CMPGT.W A-125CMPGTA A-127CMPHI A-129 CMPHIA A-131Conditional execution 5-9CONT A-133 CONTD A-135 Control instructions 2-68Control registers 3-1Convergent rounding 2-21Core Architecture 1-1 Core control registers 3-1

clearing EMR bits 3-10

exception and mode register (EMR) 3-7status register (SR) 3-1,3-2

CORES (core status) 4-38CORETP (core type) 4-39 CORETP (SCID field) B-1 CS (comparators selection) 4-55

Debug mode 4-11

DEBUGERST (debugger status information) 4-42DEBUGEV A-138

Debugging system 4-1DECA A-139DECEQ A-141DECEQA A-143DECGE A-144DECGEA A-146

DI A-148

DI (disable interrupts bit) 3-4DIS (debug interrupt status) 4-42DIV A-150

Division 2-20

DMA (direct memory access) 1-4DMAC implementation 2-26DMACSS A-153

DMACSU A-155

DOENn A-157 DOENSHn A-159 DOSETUPn A-161

DOVF (data ALU overflow bit) 3-8 DRCOUNTER (debug reason is counter) 4-40DREDCA7-0 (debug reason is EDCA7-0)4-40DREE4-0 (debug reason is EE4-0) 4-39 DRSW (debug reason is software bug) 4-39 DRTBFULL (debug reason is trace buffer) 4-39

D	E
D0-D15 data registers 2-8	ECNT_CTRL (event counter control register) 4-50
data 2-1	ECNT_CTRL register
Data ALU (data arithmetic logic unit) 1-3,2-2	ECNTEN 4-52
architecture 2-6	ECNTWHAT 4-52
arithmetic and rounding 2-17	EXT 4-51
arithmetic saturation mode 2-25	ECNT_EXT (extension counter value register) 4-53
bit-field unit 2-3,2-12	ECNT_VAL (event counter value register) 4-52
data formats 2-18	ECNTEN (event counter enable) 4-52
data shifter/limiter 2-13	ECNTWHAT (events to be counted) 4-52
multi-precision arithmetic support 2-26	ECR (EOnCE command register) 4-36
programming model 2-7	EX 4-37
rounding 2-21	GO 4-37
scaling 2-14	REGSEL 4-37
signed fractional 2-18	EDCA (address event detection channel) 4-22,4-54
signed integer 2-19	control registers (EDCAi_CTRL) 4-54
unsigned comparison 2-21	mask registers (EDCAi_MASK) 4-57
unsigned integer 2-19	reference value registers A and B (EDCAi_REFA,
Data buses 2-2	EDCAi_REFB) 4-57
Data buses (XDBA and XDBB) 2-6,2-9	EDCAEN (event detection channel (EDCAi)
Data formats 2-18	enable) 4-55
Data registers (D0-D15)2-3,2-8	EDCAi_CTRL (EDCA control registers) 4-54
accesses 2-8	ATS 4-56
Data shifter/limiter 2-13	BS 4-56
DEBUG A-137	CACS 4-56
Debug exception 4-12	CBCS 4-56

I-2 Index