I-2 Index
CCS (comparator condition selection bit s) 4-60
Change-of-flow instructions 2-68
CLB A-113
CLR A-115
CMPEQ A-117
CMPEQ.W A-119
CMPEQA A-121
CMPGT A-123
CMPGT.W A-125
CMPGTA A-127
CMPHI A-129
CMPHIA A-131
Conditional execution 5-9
CONT A-133
CONTD A-135
Control instructions 2-68
Control registers 3-1
Convergent rounding 2-21
Core Architecture 1-1
Core control registers 3-1
clearing EMR bits 3-10
exception and mode register (EMR) 3-7
status register (SR) 3-1, 3-2
CORES (core status) 4-38
CORETP (core type) 4-39
CORETP (SCID field) B-1
CS (comparators selection) 4-55
D
D0-D15 data registers 2-8
data 2-1
Data ALU (data arithmetic logic unit) 1-3, 2-2
architecture 2-6
arithmetic and rounding 2-17
arithmetic saturation mode 2-25
bit-field unit 2-3, 2-12
data formats 2-18
data shifter/limiter 2-13
multi-precision arithmetic support 2-26
programming model 2-7
rounding 2-21
scaling 2-14
signed fractional 2-18
signed integer 2-19
unsigned comparison 2-21
unsigned integer 2 -19
Data buses 2-2
Data buses (XDBA and XDBB) 2-6, 2-9
Data formats 2-18
Data registers (D0-D15) 2-3 , 2-8
accesses 2-8
Data shifter/limiter 2-13
DEBUG A-137
Debug exception 4-12
Debug mode 4-11
DEBUGERST (debugger status information) 4-42
DEBUGEV A-138
Debugging system 4-1
DECA A-139
DECEQ A-141
DECEQA A-143
DECGE A-144
DECGEA A-146
DI A-148
DI (disable interrupts bi t) 3-4
DIS (debug interrupt status) 4-42
DIV A-150
Division 2-20
DMA (direct memory access) 1-4
DMAC implementation 2-26
DMACSS A-153
DMACSU A-155
DOENn A-157
DOENSHn A-159
DOSETUPn A-161
DOVF (data ALU overflow bit) 3-8
DRCOUNTER (debug reason is counter) 4-40
DREDCA7-0 (debug reason is EDCA7-0) 4 -40
DREE4-0 (debug reason is EE4-0) 4-39
DRSW (debug reason is software bug) 4-39
DRTBFULL (debug reason is trace buffer) 4-39
E
ECNT_CTRL (event counter control register) 4-50
ECNT_CTRL register
ECNTEN 4-52
ECNTWHAT 4-52
EXT 4-51
ECNT_EXT (extension counter value register) 4-53
ECNT_VAL (event counter value register) 4-52
ECNTEN (event counter enable) 4-52
ECNTWHAT (events to be counted) 4-52
ECR (EOnCE command register) 4-36
EX 4-37
GO 4-37
REGSEL 4-37
EDCA (address event detection chan nel) 4-22, 4-54
control registers (EDCAi_CTRL) 4-54
mask registers (EDCAi_MASK) 4-57
reference value registers A and B (EDCAi_REFA,
EDCAi_REFB) 4-57
EDCAEN (event detection channel (EDCA i)
enable) 4-55
EDCAi_CTRL (EDCA control registers) 4-54
ATS 4-56
BS 4-56
CACS 4-56
CBCS 4-56