Freescale Semiconductor SC140 Instruction Formats and Opcodes, Instruction Fields, Aaa, Ccc

DSP Core Instruction Set

A.1.5.1 One-Word Low Register Prefix

Includes information on grouping, looping, and IFc (conditional execution).

Instruction Formats and Opcodes

Prefix WordsCyclesType

1W LOW	REG	0	4
PREFIX	1

Opcode

15 8 7 0

1 0 0 1 a a a 0 1 1 0 p j c c c

Instruction Fields

aaa:	Number of instruction words being grouped, including the prefix word minus one. If aaa
	equals zero, this is a NOP instruction that is not dispatched for either a single, stand-alone
	NOP, or an intra-set NOP [0	≤ aaa ≤ 7].
ccc:	Conditional execution of the entire execution set.
	In the following table, true/false relates to the state of the T bit in SR. D0, D1, D2, and D3 are
	DALU instructions. A0 and A1 are AGU instructions. The numbers relate to the relative word
	offset of the instruction from the beginning of the set.
	000—Unconditionally executed
	001—If true (D0, D2, A0) If false (D1, D3, A1)
	010—If true, all the set
	011—If false, all the set
	100—Reserved
	101—Reserved
	110—If true (D0, D2, A0), always (D1, D3, A1)
	111—If false (D0, D2, A0), always (D1, D3, A1)
p:	lpmarkB bit
	In the case of a loop with three or more execution sets, the lpmarkB bit is a one in the
	execution set that is two before the last execution set in the loop.
	Example:
	lpmarkB	;(set LA – 2)
	_last	;(set LA – 1)
		;(set LA)
	In the case of a loop with two execution sets such as SA mark, the lpmarkB bit is set in the first
	execution set of the loop.
	Example:
	_start execution_setlpmarkb
j:	_last execution_set	;(this is a loop on two execution sets)
	lpmarkA bit
	In case of a loop with more than three execution sets, the lpmarkA bit is set in the prefix of the

execution set which is at _last only if there are any SKIPLS, BREAK, CONT, CONTD to _last, or to _last-1.

A-8 SC140 DSP Core Reference Manual