Core Control Registers

Table 3-2 describes the EMR fields.

 

Table 3-2. EMR Description

 

 

 

Name

Description

Settings

 

 

 

 

 

 

R

Reserved

 

Bits 31–24

 

 

 

 

 

GP6–GP0

General Purpose Flags — Use of these bits is

 

Bits 23–17

dependent on the state of external pins. Their

 

 

function is specific to the SoC.

 

 

 

 

BEM

Big Endian Memory Bit — Indicates big endian

0 = Little endian configuration

Bit 16

or little endian memory configuration. See

1 = Big endian configuration

 

Section 2.4.1, “SC140 Endian Support,” for more

 

 

information.

 

 

This bit is dependent on the state of an external

 

 

pin. This pin is sampled at core reset.

 

 

 

 

R

Reserved

 

Bits 15–4

 

 

 

 

 

NMID

Non-maskable Interrupt (NMI) Disable Bit

0 = No NMI service executing

Bit 3

Set when an NMI service routine enters execution

1 = NMI service executing

 

such as when the NMI vector is fetched. While this

 

 

bit is set, no pending NMI requests are serviced.

 

 

The bit is cleared by an RTE instruction, or by

 

 

writing back 1 to it as explained in Section 3.1.2.1,

 

 

“Clearing EMR Bits.”

 

 

The NMI bit cannot be set by the user. It is cleared

 

 

at reset.

 

 

 

 

DOVF

DALU Overflow Bit — Indicates that an overflow

0 = No overflow or arithmetic saturation occurred

Bit 2

from 40 bits occurred during a DALU operation, or

1 = Overflow or arithmetic saturation occurred

 

that arithmetic saturation occurred in arithmetic

 

 

saturation mode (overflow from 32 bits).

 

 

Whenever there is an overflow, an exception is

 

 

generated if the OVE bit is set in the SR. Until the

 

 

bit is cleared, no new exceptions are generated.

 

 

The DOVF bit is a sticky bit. The bit is set if the

 

 

appropriate exception occurred. It can only be

 

 

cleared by writing back 1 to it as explained in

 

 

Section 3.1.2.1, “Clearing EMR Bits.”

 

 

The DOVF bit cannot be set by the user, only by

 

 

the hardware. It is cleared at reset.

 

 

If the OVE bit is set, the clearing operation should

 

 

only be performed during the overflow exception

 

 

service routine.

 

 

Due to pipeline effects, the overflow exception is

 

 

not serviced immediately after the instruction that

 

 

caused the overflow condition.

 

 

 

 

3-8

SC140 DSP Core Reference Manual

Page 108
Image 108
Freescale Semiconductor SC140 specifications Describes the EMR fields, EMR Description