5.5.5

Fast Return from Subroutines

5-36

5.6

Working Modes

5-37

5.6.1

Normal Working Mode

5-37

5.6.2

Exception Working Mode

5-37

5.6.3

Typical Working Mode Usage Scenarios

5-38

5.6.3.1

Dual-stack RTOS

5-38

5.6.3.2

Single-stack RTOS

5-39

5.6.4

Working Mode Transitions

5-39

5.6.4.1

From Exception to Normal mode

5-39

5.6.4.2

From Normal to Exception mode

5-39

5.7

Processing States

5-41

5.7.1

Processing State Change Instructions

5-41

5.7.2

Processing State Transitions

5-42

5.7.3

Execution State

5-43

5.7.4

Reset Processing State

5-43

5.7.5

Debug State

5-44

5.7.6

Wait Processing State

5-44

5.7.7

Stop Processing State

5-45

5.8

Exception Processing

5-46

5.8.1

Interrupt Vector Address

5-48

5.8.1.1

Vector Base Address Register

5-48

5.8.1.2

Programming Exception Routine Addresses

5-48

5.8.2

Return From Exception Instructions

5-49

5.8.3

Maskable Interrupts

5-50

5.8.3.1

Interrupt Priority Level

5-50

5.8.3.2

Controlling All Interrupt Sources

5-50

5.8.4

Non-Maskable Interrupts (NMI)

5-50

5.8.5

Internal Exceptions

5-50

5.8.5.1

Illegal Exception

5-51

5.8.5.2

DALU Overflow

5-52

5.8.5.3

TRAP Exception

5-52

5.8.5.4

Debug Exception

5-52

5.8.6

Exception Interface to the Pipeline

5-52

5.8.6.1

Exception Routine Fetch

5-52

5.8.6.2

Exception Mode Execution

5-53

5.8.7

Exception Timing

5-53

Chapter 6

Instruction Set Accelerator Plug-In

6.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-57 6.2 ISAP - SC140 Schematic Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-58

6.2.1 Single ISAP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-58

6.2.2 Multiple ISAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-59 6.3 ISAP instructions and instruction encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-60 6.4 ISAP Memory Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-606.5 ISAP-core register transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-61 6.6 Immediate Data Transfer to ISAP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-62

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SC140 DSP Core Reference Manual

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Freescale Semiconductor SC140 specifications Instruction Set Accelerator Plug-In