Freescale Semiconductor SC140 Trace Loops Mode Enables tracing, Trace Buffer Enable Mode Enables

Trace Unit Registers

Table 4-23. TB_CTRL Description (Continued)

Name	Description	Settings
TLOOP	Trace Loops Mode — Enables tracing	0	= Loop tracing is disabled.
Bit 5	the addresses of hardware loops. When	1	= Loop tracing is enabled.
	the bit is set, every change of flow
	resulting from a loop puts the last	For long loops, tracing includes LA, SA and optional
	address of loop (LA) into the trace		counter values.
	buffer. In the case of a long loop, the
	start address of loop (SA) is put into the	For short loops, tracing includes only the PC of the loop LA
	trace buffer after LA. If the loop has a
	number of iterations N, the LA and SA of
	the loop are written to the trace buffer
	(N-1) times. The last iteration of the loop
	is executed in normal flow. If LC = 0 or
	LC = 1, LA and SA are not written to the
	trace buffer.
TEN	Trace Buffer Enable Mode — Enables	0	= Tracing is disabled.
Bit 4	tracing. The TEN bit can be set or	1	= Trace is enabled.
	cleared directly. It can also be set when
	TB is enabled by the ES_ETB. It is
	cleared when disabled by the ES_DTB.
TMARK	Trace Mark Instruction Mode —	0	= MARK instruction is not traced.
Bit 3	Enables the trace of MARK instruction	1	= PC of MARK instruction is traced.
	execution.
TEXEC	Trace Issue of Execution Sets Enable	0	= Execution set tracing is disabled.
Bit 2	Mode — Enables tracing the addresses	1	= Execution set tracing is enabled. All other mode bits
	of every issued execution set.		should be cleared.
			Tracing includes the PC of every issued execution set.
TINT	Trace Interrupts Enable Mode — Used	0	= Interrupt tracing is disabled.
Bit 1	to enable tracing the addresses of	1	= Interrupt tracing is enabled.
	interrupt vectors. When the bit is set,		Tracing includes source PC of interrupt point, the PC
	each service of an interrupt puts the		of the interrupt vector, and optional counter values
	address of the last executed or aborted
	execution set (before the interrupt) into
	the trace buffer as well as the address of
	the interrupt vector.
TCHOF	Trace Addresses of Change-of-Flow	0	= Tracing of COF instructions is disabled .
Bit 0	(COF) Instructions Enable Mode —	1	= Tracing of COF instructions is enabled.
	Used to enable the tracing of addresses		Tracing includes source PC, destination PC and
	for execution sets containing		optional counter value.
	change-of-flow instructions. When the
	bit is set, every execution of an
	execution set containing change-of-flow
	instructions (even if the change-of-flow
	instruction is executed together with
	other instructions in the execution set)
	puts into the trace buffer the address of
	that execution set (the address of the
	first instruction in the execution set) and
	the target address of the change-of-flow
	instruction.

4-68 SC140 DSP Core Reference Manual