Freescale Semiconductor SC140 Divide Iteration Dalu, If Dn39 ⊕ Da39 =, DIV Da,Dn

DIV

DIV

Divide Iteration (DALU) DIV

Operation	Assembler Syntax
If Dn[39] ⊕ Da[39] = 1,	DIV Da,Dn
then 2 * Dn + C + (Da & $FF FFFF 0000) → Dn
else 2 * Dn + C – (Da & $FF FFFF 0000)	→ Dn

where ⊕ denotes the bitwise exclusive OR operator.

Description

DIV Da,Dn

This instruction is used iteratively to divide the destination operand Dn by the source operand Da and store the result in the destination operand Dn. The 32-bit dividend must be a positive fraction which has been sign-extended to 40-bits and stored in the full 40-bit Dn. The 16-bit divisor is a signed fraction and is stored in Da.

Each DIV iteration calculates one quotient bit using a non-restoring fractional division algorithm (see description below). After the execution of the first DIV instruction, Dn holds both the partial remainder and the formed quotient. The partial remainder occupies the high portion of Dn and is a signed fraction. The formed quotient occupies the low portion of Dn and is a positive fraction. One bit of the formed quotient is shifted into bit 0 of Dn at the start of each DIV iteration. The formed quotient is the true quotient if the true quotient is positive. If the true quotient is negative, the formed quotient must be negated. Valid results are obtained only when Dn < Da and the operands are interpreted as fractions. This condition ensures that the magnitude of the quotient is less than one (i.e., is fractional) and precludes division by zero.

The DIV instruction calculates one quotient bit based on the divisor and the previous partial remainder. To produce an N-bit quotient, the DIV instruction is executed N times, where N is the number of bits of precision desired in the quotient, 1≤N≤16. Thus, for a full-precision (16 bit) quotient, 16 DIV iterations are required. In general, executing the DIV instruction N times produces an N-bit quotient and a 32-bit remainder that has (32–N) bits of precision and whose N most significant bits are zeros. The partial remainder is not a true remainder and must be corrected (due to the non-restoring nature of the division algorithm) before it can be used. Therefore, once the divide is complete, it is necessary to reverse the last DIV operation, and restore the remainder to obtain the true remainder.

The DIV instruction uses a non-restoring fractional division algorithm that consists of the following operations (see the previous Operation definition):

1.Compare the source and destination operand sign bits: An exclusive OR operation is performed on bit 39 of Dn and bit 39 of Da.

2.Shift the partial remainder and the quotient: Dn is shifted one bit to the left. The carry bit C is moved into bit 0 of Dn. The carry bit represents the quotient bit generated by the previous DIV iteration.

A-150 SC140 DSP Core Reference Manual