Freescale Semiconductor SC140 specifications Dalu Instruction Timing, Move Instruction Timing

Instruction Timing

5.3.1.1 DALU Instruction Timing

DALU instructions are the most timing-critical instructions in the DSP algorithm kernels, taking only one cycle to execute. DALU instructions consist, among others, of the following:

•Multiply-accumulate (MAC)

•Multiply (MPY)

•ADD

•SUB

•Compare

•Shift

•Test

5.3.1.2 Move Instruction Timing

Most of the move instructions take one cycle to execute, assuming a zero-wait-state, contention-free memory. The exception is for the addressing modes requiring an arithmetic calculation of a new address: (Rn + N0), (Rn + Rm), (Rn + x), (Rn + xxxx), (SP – xx) and (SP + xxxx). These addressing modes require one additional clock cycle to calculate the address of the memory access. All the other versions of data moves are one cycle, including the versions for byte, word, two-word, long-word, four-word, and two long-word operands (signed or unsigned). Data can be moved between memory and register, or between registers.

5.3.1.3 Bit Mask Instruction Timing

The SC140 core includes various instructions for bit mask operations. These instructions are helpful when several bits need to be changed or tested at the same time. The bit mask instructions include the following:

•Bit mask set (BMSET)

•Bit mask clear (BMCLR)

•Bit mask change (BMCHG)

•Bit mask test (BMTSTS, BMTSTC)

•Bit mask test and set (BMTSET)

Bit mask instructions are a read-modify-write instruction. This means they have three steps:

1.Read the operand.

2.Change (set, clear, or change) selected bits.

3.Write the operand back to the original location.

This type of instruction takes two clock cycles to execute for the simple addressing modes, and three clock cycles for the addressing modes that require pre-calculationof the address.

Refer to Appendix A, “SC140 DSP Core Instruction Set,” for a full description of the bit mask instructions.

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