Freescale Semiconductor SC140 Pipeline Exposure, Programming Rule Notation, Grouping Rules

Programming Rule Notation

7.3 SC140 Pipeline Exposure

The SC140 has no hardware interlocks, so the pipeline is fully exposed during VLES execution. This is in direct contrast with the VLES sequencing and grouping semantics presented above, and is the motivation for the SC140 programming rules that follow. The programming rules hide the short pipeline latencies so they are not exposed in the assembly source code, saving hardware complexity and making SC140 code portable across different pipelines.

The SC140 software development tools (assembler and simulator) replace hardware interlocks with software detection of equivalent programming rules. This allows the programmer to write software that conforms to the VLES sequencing and grouping semantics defined above. The compiler code generation conforms to the programming rules by definition, since it always produces correct SC140 code.

7.4 Programming Rule Notation

Programming rules in this chapter use the following notation:

7.4.1 Grouping Rules

Grouping rules enforce the VLES grouping semantics within the same VLES by specifying that instruction “A” and instruction “B” cannot be “grouped in a VLES”. That is, “A” and “B” cannot execute in parallel.

Some grouping rules specify that instruction “A” cannot be in a VLES at a specific location. They use the notation that “A” cannot be “in a delay slot,” “in a short loop,” “at LA of the same long loop n,” or “in the first VLES of an exception service routine,” and so on.

7.4.1.1 Prefix Instructions

Prefix instructions are a unique instruction type, because they are encoded in a VLES prefix and are not dispatched to execution units. Any unique rule application is specifically noted in the rule definition.

7.4.1.2 Conditional Subgroups

Unless stated otherwise, the grouping rules in this chapter apply to the VLES as a whole regardless of any conditional instructions, IFc groups, or subgroups. Some rules apply independently to each IFc subgroup, and are specifically noted in the rule definitions. In this manual, the term “mutually exclusive subgroups” refers only to VLES having the IFT/IFF subgroups. IFT/IFA and IFF/IFA are not mutually exclusive subgroups.

7.4.1.3 Assembler Reordering

The assembler reorders instructions within a VLES for encoding efficiency. If more than one instruction in the VLES affects the carry bit C in SR, the assembler must keep the last (in assembly source order) carry-affecting instruction in each group or subgroup as last (highest word position) in its respective VLES encoding. This reordering conforms to the carry-update semantics described in Section 7.2, “VLES Grouping Semantics,” and is described in Section 5.2.5, “Instruction Reordering Within an Execution Set.”

SC140 DSP Core Reference Manual 7-3