Freescale Semiconductor SC140 EE Signals as Outputs, Detecting Entry into Debug State

EOnCE Controller Registers

4.7.6 EE Signals

EEsignals are general-purpose core interfaces which serve as input or output to the EOnCE. They can be connected off-chip or to a specific on-chip peripheral. This connection is defined by the SoC derivative. In some systems, the EE signals are not connected to an external signal.

4.7.6.1 EE Signals as Outputs

EEsignals can be used to indicate internal EOnCE events to devices outside the core. The internal signals which can be indicated are:

•Detection by the event detection channels

•Detection of entry into debug state

•Status bit of the ERCV register

•Status bit of the ETRSMT register

4.7.6.1.1 Detection by the Event Detection Channels

Each EE signal can be configured to serve as an off-core indication of an event detected by the corresponding EDCA or by EDCD. The EE signals in this case work as a toggle. This capability can be used in the following manner:

•One or more event detection channels of the EOnCE can be programmed to detect certain events.

•Each event detection channel toggles its EE signal when the detection of the desired event occurs.

•The time elapsed between the two detected events can be measured by connecting the EE signals to a logic analyzer.

If the EE pin is connected to an I/O pad of the chip, there may be limitations on the frequency of events that could be reflected on these pins due to the fact that I/O pad frequency is usually substantially lower then the core frequency. The logic definition of the behavior of the EE pins outputs assumes that the frequency of the I/O pad is no less than 4 times slower than the core frequency. In order to support this, a toggle cannot occur in two consecutive cycles. A toggle can occur in a cycle only if there was no toggle in the preceding cycle. If the frequency of the core is more than 4 times the I/O pad maximum supported frequency, then not all event sequences could be properly reflected on the pads, and some extra logic may be required between the EOnCE EE pin outputs and the I/O pads to buffer or compress events.

4.7.6.1.2 Detecting Entry into Debug State

The EE1 signal can be configured as an indication of debug state. Each time the core enters debug state, the EE1 signal is asserted. On exiting debug state, the EE1 signal is negated. This technique can be used as a debug acknowledge.

4.7.6.1.3 Status Bit of the ERCV Register

The EE3 signal can be programmed to serve as an indication that the ERCV register (read by the core) is empty. This capability provides interrupt driven transfers to the host debugger. If the EE3 signal is programmed in this way, it is asserted when the host has finished writing to the ERCV register through the JTAG. It is negated when the core finishes reading the Most Significant Part of the ERCV register.

4-44 SC140 DSP Core Reference Manual