Freescale Semiconductor SC140 specifications EOnCE Status Register ESR

		EOnCE Controller Registers
	Table 4-13. ECR Description (Continued)
Name	Description	Settings
GO	Go Command — If this bit is set, there are	0 = Inactive (no action taken)
Bit 8	two possible modes of execution:	1 = Execute one instruction
	• When used together with writing or
	reading a register (except for
	CORE_CMD), this register is first written
	or read, and then the next instruction in
	the pipeline is executed. When used
	together with the NOREG register, only
	the next instruction in the pipeline is
	executed. In this single-step mode, the
	core leaves debug state for one
	instruction cycle in order to execute the
	instruction. If the EX bit is also set, the
	core continues normal operation after
	executing the instruction.
	• When used together with writing to the
	CORE_CMD register, the instruction
	written to the CORE_CMD register is
	executed, and the core remains in debug
	state. If the EX bit is set as well, debug
	state is exited after the instruction is
	executed.
EX	Exit Command — If this bit is set, then after	0 = Remain in debug state.
Bit 7	executing any associated write or read	1 = Exit debug state.
	command, the core leaves debug state and
	resumes normal operation. When used
	together with the write or read NOREG
	command, the exit command is executed
	without writing or reading any register.
REGSEL	Register Select — Define which register is
Bits 6–0	the source or destination for the read or write
	operation. See Table 4-12 on page 4-31 for
	the EOnCE register offsets.

4.7.2 EOnCE Status Register (ESR)

The ESR is a 32-bit register. The status bits of the register indicate the status of the core as well as the reason for entering debug state or for issuing a debug exception. All bits are read-only.

Debug reason bits are set to show what caused the core to enter debug state or execute a debug exception. These bits are reset when the core leaves debug state or if the DIS bit in EMCR is reset by an interrupt service routine. After entering debug state, the appropriate bit is set when a new event occurs that could cause the core to enter debug state.

Figure 4-16 displays the bit configuration of the ESR.

	BIT 31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	CORES			PCKILL	RCV	TRSMT	TBFULL	NOCHOF		REVNO			CORETP			DRTBFULL
TYPE	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r
RESET	0	0	0	0	0	0	0	0	x	x	x	0	x	x	x	0

SC140 DSP Core Reference Manual 4-37