Core Control Registers

Table 3-1. Status Register Description (Continued)

Name

Description

 

Settings

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

S

Scaling Bit — Set when moving a result

 

 

 

 

 

 

 

 

 

 

 

 

Bit 6

from a data register (D0–D15) to

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Scaling

 

 

 

 

 

memory using a MOVES (saturated

 

 

S1

S0

 

 

S Equation

 

 

 

 

 

 

Mode

 

 

 

 

move) instruction. The scaling bit is set

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

when the absolute value of the data that

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

0

 

No scaling

 

S = (D30 XOR D29)

 

 

 

is moved to memory (after scaling and

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OR S (previous)

 

 

 

limiting) is greater than or equal to 0.25

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

and less than 0.75.

 

 

0

 

1

 

Scale down

 

S = (D31 XOR D30)

 

 

 

The logical equations of this bit, if viewed

 

 

 

 

 

 

 

 

 

OR S (previous)

 

 

 

as functions of the data in the register,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

0

 

Scale up

 

S = (D29 XOR D28)

 

 

 

are dependent on the scaling mode.

 

 

 

 

 

 

 

 

If limiting occurs during a data register

 

 

 

 

 

 

 

 

 

OR S (previous)

 

 

 

transfer to memory, the scaling bit is not

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

1

 

Reserved

 

S = Undefined

 

 

 

affected. This bit is a sticky bit and it

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

remains set until explicitly cleared.

 

 

 

 

 

 

 

 

 

 

 

 

 

This bit is cleared at core reset.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

S1–S0

Scaling Mode Bits — Specify the

 

 

 

 

 

 

 

 

 

 

 

 

Bits 5–4

scaling to be performed in the DALU

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Rounding

 

 

 

 

 

 

shifter/limiter as well as the rounding

 

 

S1

 

S0

 

 

Scaling Mode

 

 

 

 

 

 

Bit

 

 

 

 

position in the DALU MAC unit.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The shifter/limiter scaling mode affects

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

0

15

 

 

No scaling

 

 

data read from the D0–D15 registers out

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

to the data memory bus using a MOVES

 

0

 

1

16

 

 

Scale down

 

 

instruction. The scaling mode also

 

 

 

 

 

 

 

 

(1-bit Arithmetic Right

 

 

affects the calculation of the Ln bit for a

 

 

 

 

 

 

 

 

 

Shift)

 

 

class of DALU instructions. See

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

0

14

 

 

Scale up

 

 

Section 2.2.1.5, “Scaling,” and

 

 

 

 

 

 

Section 2.2.1.6, “Limiting,” for more

 

 

 

 

 

 

 

(1-bit Arithmetic Left Shift)

 

 

information.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

1

 

 

 

Reserved

 

 

The scaling mode also affects the MAC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

rounding bit position. Correct rounding is

 

 

 

 

 

 

 

 

 

 

 

 

 

maintained when different portions of the

 

 

 

 

 

 

 

 

 

 

 

 

 

registers are read out to the data

 

 

 

 

 

 

 

 

 

 

 

 

 

memory buses. For more information,

 

 

 

 

 

 

 

 

 

 

 

 

 

see Section 2.2.2.6, “Rounding Modes.”

 

 

 

 

 

 

 

 

 

 

 

 

 

During arithmetic saturation mode, the

 

 

 

 

 

 

 

 

 

 

 

 

 

scaling bits are ignored for most DALU

 

 

 

 

 

 

 

 

 

 

 

 

 

instructions. See Section 2.2.2.7,

 

 

 

 

 

 

 

 

 

 

 

 

 

“Arithmetic Saturation Mode.”

 

 

 

 

 

 

 

 

 

 

 

 

 

These bits are cleared at the start of an

 

 

 

 

 

 

 

 

 

 

 

 

 

exception service routine as well as at

 

 

 

 

 

 

 

 

 

 

 

 

 

core reset.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RM

Rounding Mode Bit — Selects the type

 

0 = Convergent rounding selected

 

 

 

 

Bit 3

of rounding performed by the DALU

 

1 = Two’s complement rounding selected

 

during arithmetic operations that involve

 

 

 

 

 

 

 

 

 

 

 

 

 

rounding. SeeSection 2.2.2.6, “Rounding

 

 

 

 

 

 

 

 

 

 

 

 

 

Modes.”

 

 

 

 

 

 

 

 

 

 

 

 

 

This bit is cleared at core reset.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SC140 DSP Core Reference Manual

3-5

Page 105
Image 105
Freescale Semiconductor SC140 Equation Mode, S1-S0 Scaling Mode Bits Specify, Rounding Mode Bit Selects the type