Architecture Overview
SC140 DSP Core Reference Manual 2-5
2.1.3 Program Sequencer Unit (PSEQ)
The PSEQ performs instruction fetch, instruction dispatch, hardware loop control, and exception
processing. The PSEQ controls the different processing states of the SC140 core. The PSEQ consists of
three hardware blocks:
•Program dispatch unit (PDU)—Responsible for detecting the execution set out of a one or two fetch
set, and dispatching the execution set’s various instructions to their appropriate execution units
where they are decoded.
•Program control unit (PCU)—Responsible for controlling the sequence of the program flow.
•Program address generator (PAG)—Responsible for generating the program counter (PC) for
instruction fetch operations, including hardware looping.
The PSEQ implements its functions using the following registers:
•PC—Program counter register
•SR—Status register
•SA0-3—Four start address registers (SA0–SA3)
•LC0-3—Four loop counter registers (LC0–LC3)
•EMR—Exception and mode register
•VBA—Interrupt vector base address register
2.1.4 Enhanced On-Chip Emulator (EOnCE)
The EOnCE module provides a non-intrusive means of interacting with the SC140 core and its peripherals
so that a user can examine registers, memory, or on-chip peripherals as well as define various breakpoints
and read the trace-FIFO. The EOnCE module greatly aids the development of hardware and software on
the SC140 core processor, EOnCE interfacing with the debugging system through on-chip JTAG TAP
controller pins. Refer to Chapter 4, “Emulation and Debug (EOnCE),” for details.
2.1.5 Instruction Set Accelerator Plug-in (ISAP) Interface
A user-defined instruction set accelerator plug-in (ISAP) module provides a means of enhancing the
SC140 basic instruction set with additional instructions. These additional instructions are executed in an
external module connected to the core. The new instructions are added to the SC140 Assembler and
Compiler via intrinsic libraries making application-specific or general-purpose functions available to the
user. A 25-bit instruction bus from the SC140 core to the ISAP enables the definition and support of a very
rich instruction set. The ISAP is also connected to the two 64-bit data buses, providing a large data
bandwidth to the main mem ory system.
2.1.6 Memory Interface
The SC140 core uses a unified memory space. Each address can contain either program information or
data. The exact memory configuration is customizable for each chip conta i ning an SC140 core. Memory
space typically consists of on-chip RAM and ROM that can be expanded off-chip. The memory system
must support two parallel data accesses. However, it may issue stalls due to its specific implementation.
Refer to Section 2.4, “Memory Interface,” for further details.
Both internal and external memory configurations are specific to each member of the SC140 family.