Freescale Semiconductor specifications SC140 DSP Core Reference Manual

4.6.4	General EOnCE Register Issues	4-34
4.7	EOnCE Controller Registers	4-36
4.7.1	EOnCE Command Register (ECR)	4-36
4.7.2	EOnCE Status Register (ESR)	4-37
4.7.3	EOnCE Monitor and Control Register (EMCR)	4-41
4.7.4	EOnCE Receive Register (ERCV)	4-43
4.7.5	EOnCE Transmit Register (ETRSMT)	4-43
4.7.6	EE Signals	4-44
4.7.6.1	EE Signals as Outputs	4-44
4.7.6.2	EE Signals as Inputs	4-45
4.7.6.3	EE Signals Control Register (EE_CTRL)	4-45
4.7.7	Core Command Register (CORE_CMD)	4-48
4.7.8	PC of the Exception Execution Set (PC_EXCP)	4-49
4.7.9	PC of the Next Execution Set (PC_NEXT)	4-49
4.7.10	PC of Last Execution Set (PC_LAST)	4-49
4.7.11	PC Breakpoint Detection Register (PC_DETECT)	4-49
4.8	Event Counter Registers	4-50
4.8.1	Event Counter Control Register (ECNT_CTRL)	4-50
4.8.2	Event Counter Value Register (ECNT_VAL)	4-52
4.8.3	Extension Counter Value Register (ECNT_EXT)	4-53
4.8.4	EC Signals	4-53
4.9 Event Detection Unit (EDU) Channels and Registers		4-54
4.9.1	Address Event Detection Channel (EDCA)	4-54
4.9.1.1	EDCA Control Registers (EDCAi_CTRL)	4-54

4.9.1.2EDCA Reference Value Registers A and B

	(EDCAi_REFA, EDCAi_REFB)	4-57
4.9.1.3	EDCA Mask Register (EDCAi_MASK)	4-57
4.9.2	Data Event Detection Channel (EDCD)	4-58
4.9.2.1	EDCD Control Register (EDCD_CTRL)	4-58
4.9.2.2	EDCD Reference Value Register (EDCD_REF)	4-61
4.9.2.3	EDCD Mask Register (EDCD_MASK)	4-61
4.10 Event Selector (ES) Registers		4-61
4.10.1	Event Selector Control Register (ESEL_CTRL)	4-61
4.10.2	Event Selector Mask Debug State Register (ESEL_DM)	4-63

4.10.3Event Selector Mask Debug Exception

Register (ESEL_DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-64

4.10.4 Event Selector Mask Enable Trace Register (ESEL_ETB) . . . . . . . . . . . . . . 4-64

4.10.5 Event Selector Mask Disable Trace Register (ESEL_DTB) . . . . . . . . . . . . . 4-65 4.11 Trace Unit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-65

4.11.1 Trace Buffer Control Register (TB_CTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . 4-65

4.11.2 Trace Buffer Read Pointer Register (TB_RD) . . . . . . . . . . . . . . . . . . . . . . . . 4-69

4.11.3 Trace Buffer Write Pointer Register (TB_WR) . . . . . . . . . . . . . . . . . . . . . . . 4-69

4.11.4 Trace Buffer Register (TB_BUFF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-69

vi SC140 DSP Core Reference Manual