Freescale Semiconductor SC140 specifications Binary Code Practices

Programming Guidelines

•Observe the immediate operand ranges as specified within the braces { } in Appendix A.2, “Instructions,” on page A-19. Operand values outside these ranges are undefined. Some specific examples are:

—ADD #u5,Dn {0 < u5 < 32}

—ASLL Da,Dn {-40 < Da[6:0] < 40}

•Observe address pointer alignments on memory accesses as specified in Table 2-19: Memory Address Alignment and within the braces { } in Appendix A.2, “Instructions.” Misaligned memory accesses are undefined. Some specific examples are:

—MOVE.L (a32),DR {0 £ a32 < 232,L}, meaning long word aligned (address is a multiple of 4).

— MOVE.4F (EA),Da:Db:Dc:Dd {0 £ EA < 232,Q}, meaning quad word aligned (address is a multiple of 8).

•Observe SP and OSP stack pointer quad alignment. The ESP and NSP registers have their three least significant bits hard-wired to zero. So SP arithmetic results that are not a multiple of 8 cannot be represented in the ESP and NSP registers. Note that MOVE-like instructions using SP with an offset to access the stack allow more general alignment based on the memory access size.

•Observe the word alignment requirement for COF destinations. Computed COF destinations (such as JMP R0) that are not a multiple of 2 are in error. Misaligned program fetches are undefined. Note that the PC register has its least significant bit hard-wired to zero.

•Observe modifier mode parameter constraints on size and offset discussed in Section 2.3.4, “Address Modifier Modes.” Using out-of-range or reserved parameter values may produce undefined results. Also observe address pointer alignments specific to the selected modifier mode.

•MOVES should be preceded by an instruction that updates the Ln-bit based on the data. Otherwise, the data moved may be modified by a Ln-bit not associated with the data.

•Do not explicitly modify the SR register to change the loop flags LFn and SLF in SR. Use the loop control instructions in Table A-14: AGU Loop Control (Including Loop COF) Instructions on page A-18.

•The SR register contains local task context such as the loop flags, T bit, etc. Always save and restore the SR register on exceptions and OS context switches.

•The EMR register contains global, not local, status bits. Do not use EMR status bits for local task context. Do not save and restore EMR on exceptions and OS context switches.

•Do not return from a subroutine with RTE/D, and do not return from an exception with RTS/D.

•If the return address on the memory stack is changed to effect a task switch, use RTSTK to bypass the RAS mechanism. Otherwise, the SC140 will return to the previous caller location if RAS is valid.

•Do not use VSL for anything other than the Viterbi algorithm. It violates the endian rules.

•Do not use “reserved” bits in registers for data storage. Always write “reserved” bits with their initial reset value (usually zero). This maintains software compatibility if a “reserved” bit is defined in the future.

7.7.2.2 Binary Code Practices

•Do not write self-modifying code (replacing portions of an application binary at run-time). It cannot be checked for errors by the assembler. It is also difficult to debug, and may not be compatible with future processor implementations.

7-50 SC140 DSP Core Reference Manual