Freescale Semiconductor SC140 Writing to the Trace Buffer, Reading the Trace Buffer Tbbuff

EOnCE Module Internal Architecture

—BREAK

—CONT, CONTD

—SKIPLS

Note that TRAP, and ILLEGAL are traced as interrupts, not as change of flow instructions.

When tracing interrupts, a source destination address pair is also traced. The source address normally reflects the PC of the last executed execution set, and the destination address reflects the PC of the interrupt vector.

There is one exception to this rule: If the interrupt occurred while the core is executing certain instructions (mainly change of flow instructions), it may be that the PC of the execution set including this instruction is traced although not actually executed. This situation is termed “PC KILL”. The debugger SW can identify this case by noting that the return PC upon returning from the exception is that of the killed PC and not that of the following execution set.

4.5.5.2 Writing to the Trace Buffer

The trace buffer is a circular buffer. A write pointer (TB_WR) points to the next free location. The pointer is incremented circularly after every trace, and cleared whenever the trace buffer is enabled.

A flag is set every time the trace buffer is full. The flag is cleared whenever the trace buffer is enabled.

4.5.5.3 Reading the Trace Buffer (TB_BUFF)

The content of the trace buffer is read either through the JTAG interface or from software using the location pointed to by the TB_RD register. The TB_RD pointer is incremented after every read access to the trace buffer, and is cleared when the trace buffer is enabled.

Due to a pre-fetch mechanism, when the user reads the location pointed to by the TB_RD register (by reading the TB_BUFF register), the TB_RD pointer is already three stages ahead. As a result of this pre-fetch mechanism, there is a restriction on reading the trace buffer. A three clock cycle delay must take place from disabling the trace buffer or writing to the read pointer until the first read access is issued to the trace buffer.

The TBFULL bit in the ESR indicates that the buffer is full, and that the contents of the trace buffer should be read. The TBFULL bit of the ESR is set when entry size minus 15 is written. When it reaches the end of the memory, the trace buffer wraps around to address zero and continues until stopped. See the description of the TBFULL bit in Section 4.7.2, “EOnCE Status Register (ESR).”

If the TBFDM in the EMCR is set, and TBFULL is being set, a debug event is generated. If the IME bit in EMCR is clear then the core enters into debug state. If the IME bit is set, a debug exception is generated. This exeption can be used by a software routine to empty the trace buffer to an external memory or device. See Section 4.7.3, “EOnCE Monitor and Control Register (EMCR),” and Section 4.6.1, “Reading or Writing EOnCE Registers Using Core Software,” for further details.

4.5.5.4 Trace Unit Programming Model

The trace unit contains the following registers, as shown in Table 4-11.

SC140 DSP Core Reference Manual 4-29