Freescale Semiconductor SC140 specifications Sequencing rules for T bit update, D.2, D.3

Programming Rules

6.8.4 Sequencing rules for T bit update

The ISAP has the ability to change the T bit as a destination of it’s instructions. The ISAP is less tightly coupled with the core, hence there the required dependency distance between The update of the T bit by the ISAP and usage by conditional core instructions is larger for non-DALU instructions.

T.2a: One VLES required between an ISAP instruction that updates the T bit and a conditional COF instruction

T.2b: 2 VLES required between an ISAP instruction that updates the T bit and a MOVET/F instruction

T.2c: 2 VLES required between an ISAP instruction that updates the T bit and an AGU instruction conditioned by IFT/F.

In addition, ISAP instructions that change the T bit or depend on it (via IFc) are subject to the same rules as are other core instructions:

T.1, D.2, D.3.

SC140 DSP Core Reference Manual 6-69