Overview of the Combined JTAG and EOnCE Interface

Table 4-2. JTAG Instructions (Continued)

B4

B3

B2

B1

B0

Instruction

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

1

0

0

HIGHZ

Selects the Bypass Register. Disables all device output drivers

 

 

 

 

 

 

and forces the output to high impedance (tri-state) as per the

 

 

 

 

 

 

IEEE specification.

 

 

 

 

 

 

 

0

0

1

1

0

ENABLE_EONCE

Selects the EOnCE registers. Allows to perform system debug

 

 

 

 

 

 

functions. Before this instruction is selected, the

 

 

 

 

 

 

CHOOSE_EONCE instruction should be activated to define

 

 

 

 

 

 

which EOnCE is going to be activated.

 

 

 

 

 

 

 

0

0

1

1

1

DEBUG_REQUEST

Selects the EOnCE registers. Forces the chosen cores EOnCE

 

 

 

 

 

 

modules into Debug state or generate a Debug exception. Before

 

 

 

 

 

 

this instruction, the ENABLE_EONCE and the

 

 

 

 

 

 

CHOOSE_EONCE instructions should be performed.

 

 

 

 

 

 

 

0

1

0

0

0

RUNBIST

Selects the BIST registers. Allows you to generate a built-in

 

 

 

 

 

 

self-test for checking the system circuitry.

 

 

 

 

 

 

 

0

1

0

0

1

CHOOSE_EONCE

Selects the EOnCE registers. Allows to select EOnCE targets in

 

 

 

 

 

 

devices with multiple EOnCE modules. This instruction is

 

 

 

 

 

 

activated before the ENABLE_EONCE and

 

 

 

 

 

 

DEBUG_REQUEST instructions.

 

 

 

 

 

 

 

0

1

1

0

0

ENABLE_SCAN

Selects the DFT registers. Allows the DFT chain registers to be

 

 

 

 

 

 

loaded by a known value or examined in the Shift_DR controller

 

 

 

 

 

 

state.

 

 

 

 

 

 

 

0

1

1

0

1

LOAD_GPR

Allows the component manufacturer to gain access to test

 

 

 

 

 

 

features of the device.

 

 

 

 

 

 

 

0

1

1

1

0

LOAD_SPR

Allows the component manufacturer to gain access to test

 

 

 

 

 

 

features of the device.

 

 

 

 

 

 

 

1

1

1

1

1

BYPASS

Selects the Bypass register. Creates a shift register path from TDI

 

 

 

 

 

 

to the Bypass Register and to TDO. Enhances test efficiency

 

 

 

 

 

 

when a component other than the current device becomes the

 

 

 

 

 

 

device under test.

 

 

 

 

 

 

 

Figure 4-2shows the TAP controller state machine, and Table 4-3scan path. The Test Mode Select (TMS) pin determines whether an register scan is performed.

shows the states associated with each instruction register scan or a data

4-4

SC140 DSP Core Reference Manual

Page 114
Image 114
Freescale Semiconductor SC140 specifications Loadgpr