Freescale Semiconductor SC140 specifications Instruction Types, Instruction Sub-types

DSP Core Instruction Set

A.1.6 Instruction Types

The SC140 instruction set is organized into the following instruction types, specified at the top of every instruction definition in this Appendix:

DALU Instructions- perform operations on the data registers D0-D15 using the DALU execution units (MAC and BFU). All DALU instructions are listed in Table A-7 and Table A-8. The architecture is described in Section 2.2.1, “DALU Architecture,” on page 2-6.

AGU Instructions- perform operations using the AGU execution units (AAU and BMU) and the program sequencer unit. All the AGU instructions are listed in Table A-9 through Table A-15. The architecture is described in Section 2.3.1, “AGU Architecture,” on page 2-31.

BMU Instructions - are a subset of AGU instructions that perform atomic read-modify-writeoperations on registers or memory locations. They execute in the BMU. All BMU instructions are listed in

Table A-12. The architecture is described in Section 2.3.6, “Bit Mask Instructions,” on page 2-49. Although the BMU instructions are a subset of AGU instructions, they are presented in this Appendix with the other types for greater visibility, and to make them easier to find.

PREFIX Instructions - support conditional execution of other instructions and NOP insertion for time and space padding. They have unique properties since their binary form is a prefix encoding. They are decoded by the dispatcher, but are not dispatched to an execution unit. All PREFIX instructions are listed in Table A-16.

A.1.6.1 Instruction Sub-types

The instruction types can be further divided into sub-types as follows:

DALU Instruction Sub-types

•Data arithmetic (including multiply-accumulate) instructions are listed in Table A-7 and described in Section 2.2.1.2, “Multiply-Accumulate (MAC) Unit,” on page 2-10.

•Logical (including bit-field) instructions are listed in Table A-8 and described in Section 2.2.1.3, “Bit-Field Unit (BFU),” on page 2-12.

AGU Instruction Sub-types

•Address arithmetic instructions (AAU) are listed in Table A-9 and described in Section 2.3.1, “AGU Architecture,” on page 2-31.

•Move instructions are listed in Table A-10 and described in Section 2.3.7, “Move Instructions,” on page 2-51.

•Stack Support instructions are listed in Table A-11 and described in Section 5.5, “Stack Support,” on page 5-32.

•Bit-Mask (BMU) instructions are listed in Table A-12 and described in Section 2.3.6, “Bit Mask Instructions,” on page 2-49.

•Non-loop change-of-flow (non-loop COF) instructions are listed in Table A-13 and described in Section 5.3.2, “Change-Of-Flow Instruction Timing,” on page 5-17.

•Loop control instructions are listed in Table A-14 and described in Section 5.4.6, “Loop Control Instructions,” on page 5-29.

—Loop change-of-flow instructions are also listed in Table A-14 and are described in Section 5.3.2, “Change-Of-Flow Instruction Timing,” on page 5-17.

•Program control instructions are listed in Table A-15 and described in Section 5.7.1, “Processing State Change Instructions,” on page 5-41.

A-12 SC140 DSP Core Reference Manual