SC140 DSP Core
Reference Manual
SC140 DSP Core Reference Manual
Table of Contents
SC140 DSP Core Reference Manual
Control Registers
SC140 DSP Core Reference Manual
Program Control
Instruction Set Accelerator Plug-In
Programming Rules
SC140 DSP Core Instruction Set
Appendix a
StarCore Registry
Appendix B
Xii
List of Figures
Xiv
List of Tables
Xvi
SC140 DSP Core Reference Manual Xvii
Xviii
List of Examples
SC140 DSP Core Reference Manual
SC140 DSP Core Reference Manual Xxi
Xxii
About This Book
Abbreviation Description
Abbreviations used in this manual are listed below
Abbreviations
ISR
Revision History
Revision Date Description
Chapter Introduction
Target Markets
Architectural Differentiation
Core Architecture Features
Typical System-On-Chip Configuration
Variable Length Execution Set Vles Software Model
SoC DSP expansion area
System expansion area
SC140 platform
Core Architecture Features
Chapter Core Architecture
Architecture Overview
Block Diagram of the SC140 Core
Data Arithmetic Logic Unit Dalu
Address Generation Unit AGU
Data Register File
Multiply-Accumulate MAC Unit
Bit-Field Unit BFU
Stack Pointer Registers
Bit Mask Unit BMU
Program Sequencer Unit Pseq
Enhanced On-Chip Emulator EOnCE
Instruction Set Accelerator Plug-in Isap Interface
Memory Interface
Dalu
Dalu Architecture
Dalu Programming Model
Limit EXT
Data Registers D0-D15
Operand Type Dn.e Dn.h Dn.l
Write to Data Registers
Read from Data Registers
Data Registers Access Width
Dalu Arithmetic Instructions MAC
Operand Type Data Width Bits
Instruction Description
DIV
NEG
Data Shifter/Limiter
Dalu Logical Instructions BFU
Scaling
Limiting
Calculating the Ln Bit
Scaling Example
Ln Bit Calculation
Scaling Mode Bits Defining the Ln bit Calculation
Limiting with the Moves Instructions
Scaling and Arithmetic Saturation Mode Interactions
Selected Special Six Other Dalu Instructions Mode
Limiting Example
10. Scaling and Limiting Interactions
11. Saturation and Rounding Interactions
Dalu Arithmetic and Rounding
Data Representation
Data Formats
Signed Fractional
Signed Fractional Signed Integer Unsigned Integer
Signed Integer
12. Two’s Complement Word Representations
Multiplication
Division
Unsigned Arithmetic
Unsigned Multiplication
13. Rounding Position in Relation to Scaling Mode
Scaling Mode High Portion Low Portion
Rounding Modes
Unsigned Comparison
Convergent Rounding No Scaling
2.6.2 Two’s Complement Rounding
Two’s Complement Rounding No Scaling
Arithmetic Saturation Mode
14. Arithmetic Saturation Example
Multi-Precision Arithmetic Support
Fractional Multi-Precision Arithmetic
Fractional Double-Precision Multiplication
Integer Multi-Precision Arithmetic
Fractional Mixed-Precision Multiplication
10. Signed Integer Double-Precision Multiplication
Viterbi Decoding Support
11. Unsigned Integer Double-Precision Multiplication
Address Generation Unit
AGU Architecture
Unit AAU
Address
Arithmetic
Address Generation Unit
AGU Programming Model
13. AGU Programming Model
Address Registers R0-R15
Stack Pointer Registers NSP, ESP
Offset Registers N0-N3
Base Address Registers B0-B7
Modifier Registers M0-M3
Shadow Stack Pointer Registers
Address Modifier Modes
Modifier Control Register Mctl
17. Address Modifier AM Bits
Address Register Indirect Modes
Addressing Modes
Register Direct Modes
Address Generation Unit
PC Relative Mode
Special Addressing Modes
Memory Access Width
Memory Access Misalignment
Access Type Aligned Address
Addressing Modes Summary
19. Memory Address Alignment
20. Addressing Modes Summary
Special
Address Register Indirect
PC Relative
Linear Addressing Mode
Reverse-carry Addressing Mode
Modulo Addressing Mode
Address Modifier Modes
15. Modulo Addressing Example
Modifier Mj Address Calculation Arithmetic
Multiple Wrap-Around Modulo Addressing Mode
21. Modulo Register Values for Modulo Addressing Mode
Arithmetic Instructions on Address Registers
23. AGU Arithmetic Instructions
Bit Mask Instructions
Bit Mask Test and Set Semaphore Support Instruction
24. AGU Bit Mask Instructions BMU
Move Instructions
Semaphore Hardware Implementation
Example of Normal Usage of the Semaphoring Mechanism
Label BMTSET.W #mask,R0 JT label
25. AGU Move Instructions
MOVE.W
16. Integer Move Instructions
17. Fractional Move Instructions
Memory Interface
18. Bit Allocation in MOVE.L D0.eD1.e
1 SC140 Endian Support
1.1 SC140 Bus Structure
Memory Organization
20. Basic Connection between SC140 Core and Memory
Representation Type Value
Data Moves
26. Data Representation in Memory
22. Data Transfer in Big and Little Endian Modes
Multi-Register Moves
Address Data
Multi-Register Transfer in Big and Little Endian Modes
Instruction Word Transfers
25. Instruction Moves in Big and Little Endian Modes
Memory Access Behavior in Big/Little Endian Modes
Example MOVE.L D0.ED1.E, A0
Example MOVE.2L D0D1, R0
Example MOVE.F D0, R0
Example MOVE.2F D0D1, R0
Example VSL.4W D2D6D1D3, R0 + N0
D6 =
Example VSL.4F D2D6D1D3, R0 + N0
Example VSL.2W D1D3, R0 + N0
Example Push D0
Example Push D0 Push D1
Example BMSET.W #$1234, A0
Data =
31. Control Instructions in Big and Little Endian Modes
Instruction Register Operands Big Little Endian
Core Control Registers
Status Register SR
Status Register Description
Name Description Settings
Describes the various SR bits
I2-I0 Interrupt Mask Bits Reflect
Exceptions
Overflow Exception Enable Bit
Disable Interrupts Bit When this bit
Exception Mode Bit Selects
Reserved
Equation Mode
S1-S0 Scaling Mode Bits Specify
Scaling Mode Bit
Rounding Mode Bit Selects the type
Name Description Settings Arithmetic Saturation Mode Selects
Exception and Mode Register EMR
Exception and Mode Register EMR
Describes the EMR fields
EMR Description
Ilst
Illegal Execution Set Indicates whether an
PLL and Clock Registers
Clearing EMR Bits
Bmclr #$fffb,EMR.L
Example 3-1. Clearing an EMR Bit
Emulation and Debug EOnCE
Debugging System
Jtag Interface Signal Descriptions
Signal Name Signal Description
Overview of the Combined Jtag and EOnCE Interface
Cascading Multiple SC140 EOnCE Modules in a SoC
Jtag Scan Paths
Jtag Instructions
Loadgpr
TAP Controller State Machine Jtag Scan Paths
Select-DR Scan Path Select-IR Scan Path
Activating the EOnCE Through the Jtag Port
Enabling the EOnCE Module
Debugrequest and Enableeonce Commands
Reading/Writing EOnCE Registers Through Jtag
Reading and Writing EOnCE Registers Via Jtag
EOnCE register write operation through Jtag
EOnCE register read capture operation through Jtag
EOnCE Signals
EOnCE Signals Jtag Signals
Main Capabilities of the EOnCE Module
Core Interface
EOnCE Dedicated Instructions
Debug State
Software Downloading
Debug Exception
Executing an Instruction while in Debug State
Software Downloading
Event type Occurs when
EOnCE Events
EOnCE Event Types
EOnCE Actions
Event and Action Summary
EOnCE Event and Action Summary
Event type
EOnCE Controller
EOnCE Enabling and Power Considerations
EOnCE Module Internal Architecture
Command Register
Transmit Register Update Signal from the TAP Controller
Address Monitor and Control Register
Address Control Decoder Logic Receive Register
Event Counter
Shows a block diagram of the event counter
Event Counter Register Set
Event Detection Unit EDU
EE5..0
Address Buses
XDBxx Data Buses
EventD Event0 Event1 Event2 Event5 Count event
Address Event Detection Channel Edca
EEi
Edca Register Set
Data Event Detection Channel Edcd
Event External Event 6,7 Count Event
EventD
Edcd register set is shown below
Event Selector ES
Optional External Event Detection Address Channels
EE40 ES block diagram is shown in Figure
Trace Unit
Event0..Event5 External Event6, Event7 EventD Count event
10. Event Selector Register Set
EOnCE Module Internal Architecture
Trace Buffer TB Off-Core
Change of Flow and Interrupt Tracing
Change of Flow
Trace Unit Programming Model
Writing to the Trace Buffer
Reading the Trace Buffer Tbbuff
EOnCE Register Addressing
11. Trace Buffer Register Set
Offset
12 displays the EOnCE register addressing offsets
12. EOnCE Register Addressing Offsets
EDCA4REFA
Reading or Writing EOnCE Registers Using Core Software
Real-Time Jtag Access
General EOnCE Register Issues
Real-Time Data Transfer
EOnCE Register Addressing
EOnCE Command Register ECR
Read/Write Command Specifies
EOnCE Controller Registers
13 describes the ECR fields
16 displays the bit configuration of the ESR
EOnCE Status Register ESR
Name Description
14 describes the ESR fields
14. ESR Description
Section
DREE3
EOnCE Monitor and Control Register Emcr
15 describes the Emcr fields
15. Emcr Description
Name Description Reserved
Debugerst
EOnCE Receive Register Ercv
EOnCE Transmit Register Etrsmt
EE Signals
EE Signals as Outputs
Detection by the Event Detection Channels
Detecting Entry into Debug State
EE Signals as Inputs
EE Signals Control Register Eectrl
16. Eectrl Description
Eeddef
EE2DEF
Core Command Register Corecmd
Length control bits are described in -17, below
17. Length Control Bits
Length Control Bits Description
PC of the Exception Execution Set Pcexcp
PC of the Next Execution Set Pcnext
PC of Last Execution Set Pclast
PC Breakpoint Detection Register Pcdetect
Event Counter Registers
Event Counter Control Register Ecntctrl
Extended Mode of Operation Bit
18 describes the Ecntctrl fields
18. Ecntctrl Description
Reserved for Test
Events to be Counted Determines
Event Counter Enable Used to
Event Counter Value Register Ecntval
EC Signals
Extension Counter Value Register Ecntext
Event Detection Unit EDU Channels and Registers
Address Event Detection Channel Edca
Edca Control Registers EDCAiCTRL
19 describes the EDCAiCTRL fields
Event Detection Channel EDCAi
Comparators Selection Used to
Comparator a Condition Selection
Access Type Selection These bits
Comparator B Condition Selection
Edca Reference Value Registers a and B EDCAiREFA, EDCAiREFB
Edca Mask Register EDCAiMASK
Data Event Detection Channel Edcd
Edcd Control Register Edcdctrl
20 describes the Edcdctrl fields
20. Edcdctrl Description
Access Width Selection
AWS
Access Type Selection The ATS bit
Comparator Condition Selection
Event Selector ES Registers
Event Selector Control Register Eselctrl
Edcd Reference Value Register Edcdref
Edcd Mask Register Edcdmask
Eselctrl fields are described in Table
21. Eselctrl Description
24 displays the bit configuration of Eseldm
Event Selector Mask Debug State Register Eseldm
Event Selector Mask Enable Trace Register Eseletb
Event Selector Mask Debug Exception Register Eseldi
Trace Buffer Control Register Tbctrl
Event Selector Mask Disable Trace Register Eseldtb
Trace Unit Registers
This mode is usefull only with the Tcount mode
22. Allowed tracing mode combinations
Trace mode
Upon a trace event, trace the counter value Ecntval
Trace Buffer Counter Mode
Tbctrl fields are described in the following table
23. Tbctrl Description
Trace Buffer Extension Counter
Trace Loops Mode Enables tracing
Trace Buffer Enable Mode Enables
Trace Mark Instruction Mode
Trace Issue of Execution Sets Enable
Trace Buffer Register Tbbuff
Trace Buffer Read Pointer Register Tbrd
Trace Buffer Write Pointer Register Tbwr
Trace Unit Registers
Chapter Program Control
Pipeline
Instruction Pipeline Stages
Illustrates the five instruction pipeline stages
Pipeline Example
Pipeline Stages Overview
Instruction Cycle Operation
Pipeline Stage Description
Address Generation
Instruction Pre-Fetch and Fetch
Instruction Dispatch
Example 5-1. Four SC140 Instructions in an Execution Set
Instruction Grouping
Execution
Grouping Types
Instruction Grouping Methods
Serial Grouping
Prefix Grouping
Prefix Types
Two-Word Prefix
Conditional Execution
One-Word Low Register Prefix
For example
Prefix Instructions
Assembly Syntax Meaning
Prefix Selection Algorithm
Low Register Prefix Selection Algorithm
Instruction Reordering Within an Execution Set
Example 5-4. Conditional Vles Having Two Subgroups
Example 5-5. Set of 2 Two-word Instructions Requiring a NOP
Instruction Timing
Sequential Instruction Timing
Instruction Categories Timing Summary
Dalu Instruction Timing
Move Instruction Timing
Bit Mask Instruction Timing
Compare Shift Test
Non-Loop Change-of-Flow Instructions
Example 5-6. Delayed Change-of-Flow and Its Delay Slot
Change-Of-Flow Instruction Timing
Direct, PC-Relative, and Conditional COF
Loop Change-Of-Flow Instructions
Delayed COF
COF Execution Cycles
Example 5-7 shows a case when a stall cycle is added
Highest cycle count of instructions grouped with Call
Number of Cycles Needed by Change-of-Flow Instructions
Example 5-7. Subroutine Call Timing
Memory Access Timing
Memory Access Examples
MOVE.L
Example 5-8. Parallel Execution of Two Move Instructions
Implicit Push/Pop Memory Timing
Memory Stall Conditions
Loop Start Address Registers SAn
Hardware Loops
Loop Programming Model
Status Register SR Loop Flag Bits
Loop Notation and Encoding
Loop Counter Registers LCn
Loop Initiation and Execution
Lpmarka and Lpmarkb Bits in Short and Long Loops
Loop Type
Location Functionality
Loop Nesting
Loop Iteration and Termination
Loop Control Instructions
10 lists the loop instructions
10. Loop Control Instructions
Instruction Operation
Example 5-14. Short Loop, Two Execution Sets
Example 5-13. Long Loop Disassembly
Example 5-12. Long Loop
Example 5-16. Nested Loop
Following is an example of a nested loop
Example 5-15. Short Loop, One Execution Set
1 SC140 Single Stack Memory Use
Stack Support
Loop Timing
2 SC140 Dual Stack Memory Use
Shows the stack structure
Stack Support Instructions
11. Stack Push/Pop Instructions
12. Even and Odd Registers
Even Register De File Odd Register Do File
Addressing Mode Description
Shadow Stack Pointer Registers
13. Stack Memory Map
14. Stack Move Instructions
Fast Return from Subroutines
Normal Working Mode
Exception Working Mode
Working Mode EXP bit Active SP
Working Modes
Typical Working Mode Usage Scenarios
Dual-stack Rtos
Working Mode Transitions
From Exception to Normal mode
From Normal to Exception mode
Single-stack Rtos
Working Modes
16. Processing State Change Instructions
Processing States
Processing State Change Instructions
10. Core State Diagram
Processing State Transitions
Reset Processing State
Execution State
17. Processing State Transitions
Processing State Transitions Description
Wait Processing State
Stop Processing State
18. Exit Wait Processing State due to an Interrupt or NMI
Exception Processing
SC140
11. Core-PIC Interface
Programming Exception Routine Addresses
Interrupt Vector Address
Vector Base Address Register
Exception Address Priority Type Description Offset Highest
Return From Exception Instructions
19. Exception Vector Address Table
Maskable Interrupts
Non-Maskable Interrupts NMI
Internal Exceptions
Interrupt Priority Level
Illegal Execution Set
Illegal Exception
Illegal Instruction
Exception Interface to the Pipeline
Dalu Overflow
Trap Exception
Debug Exception
Exception Mode Execution
Exception Timing
20. Exception Pipeline
Example 5-17. Basic Exception Timing
Exception Processing
12 provides a flow chart for Example
21. Pipeline Example
Instruction Set Accelerator Plug-In
Introduction
Isap SC140 Schematic Connection
Single Isap
Data Memory
SC140Core
Core to Multiple Isap Connection Schematic
Multiple Isap
Isap Memory Access
Isap instructions and instruction encoding
Isap Encoding Fields
Binary Encoding Words Bits
To understand this, look at the following lines of code
Example 6-1. Isap memory access
ISAP-core register transfers
Immediate Data Transfer to Isap registers
Following line of code
Example 6-2. ISAP-Core register transfers
Example 6-3. ISAP-Core register transfers
Core Assembly Syntax with an Isap
Identification of Isap instructions
Working with One Isap
Vles that uses an implicit Isap ID string
One Isap in a Multi-Line Vles
Working with Multiple ISAPs
One Isap in a Single-Line Vles
Example 6-5. Multiple Isap coding
An Example of the Definition Flexibility of an Isap
Multiple ISAPs in a Multi-Line Vles
Example 6-6. Conditional Execution Example
Example 6-7. Conditional Execution Example
Programming Rules
Isap Functions that Interact With the Core
Grouping rules for explicit Isap instructions
Rules for implicit AGU instructions
Sequencing rules for T bit update
D.2, D.3
Programming Rules
Vles Sequencing Semantics
Vles Grouping Semantics
Vles Grouping Semantics
Grouping Rules
SC140 Pipeline Exposure
Programming Rule Notation
Sequencing Rules
Register Read/Write
Status Bit Updates
Instruction Words
MOVE-like Instructions
Register Aliasing
Delayed COF Instructions
Delay Slot
AGU Arithmetic Instructions
Change-Of-Flow Destinations
Enabled Loop
Static Programming Rules
Hardware Loops
Hardware Loop Detection
General Grouping Rules
Rule G.G.1
Rule G.G.2
Rule G.G.3
Rule G.G.4
Example 7-5 Duplicate PC Destinations
Example 7-6 Duplicate Address Pointer Register Destinations
Example 7-7 Duplicate Stack Pointer Destinations
Rule G.G.4 Exceptions
Example 7-8 Duplicate Register Destinations
Example 7-9 Duplicate SR/EMR Register Destinations
Example 7-10 Duplicate Status Bit Destinations
Prefix Grouping Rules
Rule G.G.5
Following rules only apply to prefix-grouped Vles
Example 7-15. Dalu Register Use Exceeds Four Times
Example 7-17 Two-Word Instructions Exceed Two
Rule G.P.1
Example 7-16 Vles Extension Words Exceed Two
Rule G.P.3
Rule G.P.4
Rule G.P.5
Example 7-18. Vles Has Mutually Exclusive Instructions
Rule G.P.6
Rule G.P.7
Example 7-20. Data Source Use of Nn and Mn Registers
Example 7-21. IFc Having Two Subgroups
Example 7-24. Isap instructions in same IFc group
Rule G.P.8
Rule G.P.9
Example 7-25. Mctl Write to R0-R7 Use
AGU Rules
Rule A.1
Example 7-26. Rn, Nn, Mn Write to AGU Use
Rule A.2
Rule A.3
Example 7-28. LCn Write to MOVE-like Use
Rule A.4
Example 7-27. Rn or Nn Write to MOVE-like Use
Delayed COF Rules
Example 7-29. Nmid Update to EMR Read
Example 7-30. Instructions in a Delay Slot
Rule A.7
Example 7-31. Instructions in a Rted Delay Slot
Example RTE/D with SR Updates
Rule D.2
Rule D.3
Rule D.4
Rule D.5
Rule D.5a
Rule D.6
Status Bit Rules
Rule D.8
Rule D.9
Rule T.1
Rule T.2.a
Rule T.2.b
Rule T.2.c
Rule SR.2
Static Programming Rules
Example 7-43. SR Write to SR Status Bit Use
Rule SR.4
Example 7-44. SR Write to SR Status Bit Update
Rule SR.3
Rule SR.4a
Example 7-45. Dovf Update to SR Read or Write
Example 7-46. Dovf Update grouped with Move-like SR updates
Loop Nesting Rules
Rule SR.7
Rule L.N.1
DI and EI DOENn and DOENSHn
Rule L.N.2
Rule L.N.3
Example 7-49. Nested Loops with Ordered Index
Example 7-50. Nested DOENn/DOENSHn Instructions
Example 7-52. Loopend between Doen and Loopend
Example 7-53. Changing a loop type
Loop LA Rules
Rule L.L.1
Rule L.L.2
Example 7-54. Instructions at the End of Long Loops
Rule L.L.3
Rule L.L.4
LA of a short loop cannot be at LA-1 of a long loop
Example 7-56. Instructions in Short Loops
Loop Sequencing Rules
Rule L.L.5
Rule L.L.6
Rule L.D.1
Rule L.D.3
Rule L.D.5
Rule L.D.6
Example 7-60. LCn Write at the Start of Short Loop n
Rule L.D.9
Rule L.D.7
Rule L.D.8
Loop COF Rules
Rule L.C.1
Rule L.C.2
Rule L.C.3
Example 7-68. Bc/Jc at LA-3 of a Long Loop
Rule L.C.5
Bc or Jc instruction is not allowed at LA-3 of a long loop
Rule L.C.7
Example 7-69. Loop COF Destination in the Same Loop
Rule L.C.9
Rule L.C.10
Example 7-70. Loop COF at End of Nested Long Loops
Example 7-71. Subroutine Call to End of Loops
General Looping Rules
Rule L.C.11
Rule L.C.12
Rule L.G.3
Dynamic Programming Rules
AGU Dynamic Rules
Rule L.G.5
Rule A.2a
Memory Access Rules
Rule A.5
Rule A.6
Rule D.7
RAS Rules
Loop Rules
Rule J.4
Rule L.N.6
Example 7-83. A.2 from a Delay Slot to a COF Destination
Rule Detection Across COF Boundaries
Cycle-Based COF Rules
Example 7-82. SR.2 Across a COF Boundary
VLES-Based COF Rules
Example 7-85. EMR access at the start of an exception
Rule Detection Across Exception Boundaries
Rule SR.2a
Rule SR.4b
Rule A.1a
Example 7-86. Mctl Write to R0-R7 Use
COF destination cannot be a delay slot
Programming Guidelines
Rule J.1
Rule J.2
Rules Not Detected Across COF Boundaries
Good Programming Practices
Source Code Practices
Rule J.5
Binary Code Practices
Software Development Practices
Lpmark Rules
Lpmark Instruction Type
Static Programming Rules
Dynamic Programming Rules
General Grouping Rules
Prefix Grouping Rules
Loop Nesting Rules
Loop LA Rules
Lpmark Rule L.L.2
Lpmark Rule L.L.3
Lpmark Rule L.L.5
Example 7-93. Active LCn Write at the End of Long Loops
Loop Sequencing Rules
Lpmark Rule L.L.6
Lpmark Rule L.D.2 + L.D.3
Lpmark Rule L.D.6
Loop COF Rules
Lpmark Rule L.C.2
COF instructions are not allowed at LPB of a long loop
Example 7-97. Active LCn Read at the Start of a Loop
Example 7-99. Bc/Jc at the Start of a Loop
Lpmark Rule L.C.3 + L.C.5
Example 7-98. COF Instructions at LPB of a Long Loop
Lpmark Rule L.C.9
Lpmark Rule L.C.10
Example 7-100. Loop COF at End of Nested Long Loops
Example 7-101. Subroutine Call to End of Loops
Rule Detection Across Exception Boundaries
Lpmark Programming Guidelines
General Looping Rules
Lpmark Rule L.C.1
Example 7-104. COF Destination to Loop Delay Slots
NOP Definition
Grouping Examples
Is encoded as
Is assembler mapped to the IFT prefix and encoded as
Is assembler mapped to the IFF prefix and encoded as
Is encoded ignoring the NOP subgroup as
NOP Definition
Appendix a SC140 DSP Core Instruction Set
Convention Definition
Conventions
Table A-1. Instruction Conventions
Table A-2. Operations Syntax
Table A-3. Register Abbreviations
Operator Description
Abbreviation Register Name
Table A-4. Assembler Syntax
Brackets as Isap indicators
Brackets as address indicators
Addressing Mode Notation
Table A-5. Addressing Mode Notation for the EA Operand
Table A-6. Addressing Mode Notation for the ea Operand
Addressing Mode Definition Notation in Instruction Field
Definition for the field is
Data Representation in Memory for the Examples
Encoding Notation
Prefix Word Encoding
Instruction Formats and Opcodes
Instruction Fields
Aaa
Ccc
Example, 2-w prefix + 2 grouped instruction words, aaa =
If true D0, D2, A0, if false D1, D3, A1
If true, all the set
Prefix Words Cycles Type
Last, or to last-1 Example
First execution set of the loop
High data register is used for the op3 field E3 is set
High data register is used for the op1 field E2 is set
DSP Core Instruction Set
Instruction Types
Instruction Sub-types
Table A-7. Dalu Arithmetic Instructions MAC
Table A-8. Dalu Logical Instructions BFU
Table A-9. AGU Arithmetic Instructions
Table A-10. AGU Move Instructions
Table A-11. AGU Stack Support Instructions
Table A-12. AGU Bit-Mask Instructions BMU
Table A-13. AGU Non-Loop Change-of-Flow Instructions
Table A-15. AGU Program Control Instructions
Table A-16. Prefix Instructions
Instruction Definition Layout
Inst
Instructions
ABS
Single Source/Destination Data Register
Instruction
ADC
Add Long With Carry Dalu
Dc + Dd + C → Dd
ADC Dc,Dd
Dc,Dd Data Register Pairs
Register/Memory Address Before
ADD
Add Dalu
Operation Assembler Syntax
Add d0,d1,d2
Add d1,d0,d2
#u5
Da,Db
Da,Da Data Register Pairs
Add2 d0,d1
ADD2
Add Two 16-Bit Values Dalu
JJJ
Single Source Data Register
Adda
Add AGU
Adda #u5,Rx
Adda #s16,rx,Rn
Adda r0,r1
Address Register
#s16
Rrrr AGU Source Register
AGU Source/Destination Register
ADDL1A Add With One-Bit Arithmetic Shift Left ADDL1A
Source Operand AGU
Addl1a r0,r1
Rx1 + Rx → Rx
ADDL1A rx,Rx
ADDL2A Add With Two-Bit Arithmetic Shift Left ADDL2A
Addl2a r0,r1
Rx2 + Rx → Rx
ADDL2A rx,Rx
ADDL2A rx,Rx
ADDNC.W
Add Without Changing ADDNC.W
Carry Bit Dalu
Addnc.w #$ca3e,d1,d2
Instruction Words Cycles Type
ADR
Add and Round Dalu
Adr d3,d4
RndDa + Dn → Dn
ADR Da,Dn
Bitwise and Dalu
#0u16,Da,Dn
#u16$0000,Da,Dn
Da,Dn
#$ff2e0000,d2,d1
D2,d1
#$0ff2e,d2,d1
#u16
#0u16
#u16$0000
#$a70e,d1.h
#u16 DR.L → DR.L
#u16 DR.H → DR.H
#u16,DR.L
Data/Address Register
Cycles Type Opcode
AND.W #u16,Rn
AND.W #u16,SP-u5
AND.W #u16,a16
AND.W #u16,SP+s16
And.w #$54a1,r7
A16
S16
ASL
Asl d0,d1
Da 1→ Dn
ASL Da,Dn
ASL Da,Dn
ASL2A
Asl2a r0
Rx2 → Rx
ASL2A Rx
Asla
Asla r0
Rx1 → Rx
Asla Rx
Asll
Multiple-Bit Arithmetic Shift Left Dalu
Asll #u5,Dn
Asll Da,Dn
Asll d0,d1
Asll
Aslw
Word Arithmetic Shift Left 16 Bits Dalu Aslw
Aslw d0,d1
Da16 → Dn
Aslw Da,Dn
ASR
Asr d5,d3
Da1 → Dn
ASR Da,Dn
Register/Memory Address Before After
Asra Rx
Asra
Asra r2
Asrr
Multiple-Bit Arithmetic Shift Right Dalu
Asrr #$3,d5
Asrr d3,d5
#u5
Asrw d5,d0
Asrw Da,Dn
Asrw Da,Dn
If T==0, then PC + displacement → PC
Branch If False AGU
BF lbl
BF label
Displacement label
Instruction Words Cycles1 Type Opcode
BFD Branch If False Using a Delay Slot AGU Operation
BFD
BFD lbl
BFD label
Label Displacement
Bmchg
~C1.Hi → C1.Hi i denotes bits=1 in #u16
~C1.Li → C1.Li
~DR.Hi → DR.Hi
Control Registers
Bmchg #$f0f0,d1.h
Clears the Ln bit in the destination data register
Iiiiiiiiiiiiiiii 16-bit unsigned immediate data
BMCHG.W
Bit-Masked Change a
Bmchg.w #$661f,$800c
BMCHG.W #u16,SP-u5
Bit signed SP address offset
Bmclr Bit-Masked Clear a 16-Bit Operand BMU Bmclr Operation
Bmclr #u16,C1.H
Bmclr #u16,C1.L
Bmclr #u16,DR.H
Bmclr #$b646,d7.l
#u16
Bit Operand in Memory BMU Operation Assembler Syntax
BMCLR.W
Bit-Masked Clear a
BMCLR.W #u16,SP-u5
Bmset #u16,C1.H
Bmset #u16,C1.L
Bmset #u16,DR.H
Bmset #u16,DR.L
Bmset #$2436,d1.l
BMSET.W
Bit Operand in Memory BMU
$800C
Bmset.w #$f111,$800c
Register/Memory Address Before Immediate
Bmtset
Bmtset #$111f,d1.l
Bmtset #u16,DR.H
Bmtset #u16,DR.L
Bmtset #$4238,d4.l
BMTSET.W
Bit-Masked Test and Set a BMTSET.W
Bmtset.w #$4328,$c
BMTSET.W #u16,SP-u5
Bmtstc
Bmtstc #$8a59,d7.h
$0$0024A60000 $00E40000
BMTSTC.W
BMTSTC.W #u16,SP-u5
BMTSTC.W #u16,SP+s16
BMTSTC.W #u16,Rn
Bmtstc.w #$8A59,r0
BMTSTC.W #u16,SP-u5
Bmtsts
Bmtsts #u16,C1.L
Bmtsts #u16,DR.H
Bmtsts #u16,DR.L
Bmtsts #$24a6,d7.h
BMTSTS.W
BMTSTS.W #u16,SP-u5
BMTSTS.W #u16,SP+s16
BMTSTS.W #u16,Rn
Bmtsts.w #$0428,r0
BMTSTS.W #u16,SP-u5
PC + displacement → PC
BRA
Branch AGU
BRA label
AAAAAAAAAA0
Source Code Comments
Brad
Brad label
$0000 000A $0000 000E
PC + displacement → PC
Break
Break label
→ LFn
Encoding is the displacement with bit
BSR
Branch to Subroutine AGU
Status and Conditions Changed by Instruction None Example
Bsr label
BSR
Bsrd label
PC + displacement → PC, next* PC→RAS
Next* PC → SP SR → SP + 4 SP + 8 → SP
Bsrd label
If T==1, then PC + displacement → PC
Branch If True AGU
BT lbl
BT label
Register/Memory Address Before BT After
BTD Branch If True Using a Delay Slot AGU Operation
BTD
BTD lbl
BTD label
$0035 $0000 $0006 $002A $001A $0016
CLB
Count Leading Bits Dalu
Clb d3,d7
CLB Da,Dn
CLB Da,Dn
CLR
Clear a Data Register Dalu
Clr d1
→ Dn
Destination Data Register
Source Data Register
Cmpeq
Compare for Equal Dalu
Cmpeq d2,d3
If Da == Dn, then 1→ T, else 0 → T
118
CMPEQ.W
CMPEQ.W Compare for Equal Dalu
Cmpeq.w #$5,d3
CMPEQ.W #u5,Dn
CMPEQ.W
Cmpeqa Compare for Equal AGU Cmpeqa Operation
Cmpeqa r1,r2
If rx == Rx, then 1 → T, else 0 → T
Cmpeqa rx,Rx
Cmpeqa rx,Rx
Cmpgt
Compare for Greater Than Dalu
Cmpgt d2,d3
Dn Da → T
124
CMPGT.W
Cmpgt.w #$8002,d2
CMPGT.W #u5,Dn
CMPGT.W #s16,Dn
CMPGT.W #u5,Dn
Cmpgta
Compare for Greater Than AGU Cmpgta
Cmpgta r2,r3
Rx rx → T
Cmpgta rx,Rx
Cmphi
Unsigned Compare for Higher Dalu Cmphi
Cmphi d1,d0
Cmphi Da,Dn
130
Cmphia
Unsigned Compare for Higher AGU Cmphia
Cmphia r0,r1
Cmphia rx,Rx
Cmphia rx,Rx
Cont
Continue to the Next Loop Iteration AGU
Label
Label
Cycles1 Type Opcode
Contd
Contd label
Cycles1 Type
Debug
Enter Debug Mode AGU
Debug
Signal a Debug Event AGU Debugev
Debugev
Deca
Decrement a Register AGU
Deca r0
Rx 1 → Rx
Bit unsigned immediate data = 1, set by the assembler
Deceq Dn
Deceq d7
Dn 1 → Dn if Dn==0, then 1→ T, else 0 → T
142
Deceqa Decrement and Set T If Equal Zero Deceqa
Deceqa r0
Rx 1 → Rx if Rx==0, then 1 → T, else 0 → T Deceqa Rx
Deceqa Rx
Decge
Example decge
Dn 1 → Dn Dn≥0 → T
Decge Dn
SC140 DSP Core Reference Manual 145
Decgea
Decgea r4
Rx 1 → Rx Rx ≥ 0 → T
Decgea Rx
Decgea Rx
Determines execution working mode
SR19 Set disable interrupt bit
→ DI
SR18
Page
DIV
Divide Iteration Dalu
If Dn39 ⊕ Da39 =
Then 2 * Dn + C + Da & $FF Ffff 0000 → Dn
Div d2,d1
DIV Da,Dn
Dmacss
Dmacss d2,d3,d5
Dn16 + Dc.H * Dd.H → Dn
Dc signed, Dd signed
Dmacss Dc,Dd,Dn 1 1
Dmacsu d2,d3,d5
Dmacsu Multiply Signed By Unsigned and Dmacsu
Accumulate With Right Shifted Data Register Dalu
156
Do Enable Long Loop AGU
Doen2 d0
DOENn #u6
DOENn #u16
Loop Identifier
#u6
Do Enable Short Loop AGU DOENSHn
Doensh2 d0
DOENSHn #u6
DOENSHn #u16
$00E4 $A0E4
Setup Long Loop DOSETUPn
Dosetup1 label
PC + displacement → SAn
DOSETUPn label
Encoding is the displacement with
SR19 Clears disable interrupt bit
→ DI
164
EOR
Bitwise Exclusive or Dalu
Eor d4,d5
Da ⊕ Dn → Dn
EOR Da,Dn
EOR #u16,DR.H
Eor #$5,d5.l
EOR #u16,DR.L
EOR #u16,DR.L EOR #u16,DR.H
EOR.W
Bitwise Exclusive or on
Eor.w #$aaaa,r0
Extract
Extract Extract Signed Bit Field Dalu
Extract #$c,#$e,d2,d4
Extract #U6,#u6,Db,Dn
Jjj Single Source/Destination Data Register
Extractu
Extractu Extract Unsigned Bit Field
Extractu #$c,#$e,d2,d4
Extractu #U6,#u6,Db,Dn
Extractu #U6,#u6,Da,Dn
Iaddnc.w #$a002,d2
IADDNC.W #s16,Dn
Conditionally Execute a Group or Subgroup Prefix IFc
If T == Then execute group/subgroup
Else treat as NOP If T == Then execute group/subgroup
Else treat as NOP Execute group/subgroup unconditionally
Ift move.w #$ffff,d0
Ccc Conditional execution of the entire execution set
Illegal
Illegal
Imac
Imac d4,d5,d6
Dn ± Da.L * Db.L → Dn
Imac ±Da,Db,Dn
Imac -d4,d5,d6
Accumulation Notation
182
Dn + Da.L * Db.H → Dn
Imaclhuu Da,Db,Dn
Imaclhuu Da,Db,Dn
Imacus
Integer Multiply Accumulate
Unsigned By Signed Dalu Operation Assembler Syntax
Imacus d3,d4,d0
$0002 x -64 $FFC0 -128 $FF80 +0 $0000 -128 $FF80
Impy
Integer Multiply Dalu
Da.L * Db.L → Dn
Impy Da,Db,Dn
D1,D1 D3,D3 D5,D5 D7,D7
IMPY.W #s16,Dn
Impy.w #$fffe,d3
#s16 * Dn.L → Dn
+16
Impyhluu
Integer Multiply Upper Impyhluu
Impyhluu d4,d3,d0
Da.H * Db.L → Dn
Impyhluu Da,Db,Dn
Impysu
Impysu d3,d5,d1
Impysu Da,Db,Dn
Register Bit Name Description Address
Impysu Da,Db,Dn
Impyuu Da,Db,Dn
Impyuu
Impyuu d5,d3,d1
196
INC
INC Increment a Data Register By One Dalu Operation
Inc d0
INC Dn
Inc d15
INC.F Dn
Inc.f d15
Dn + $0000010000 → Dn
INC.F Dn
Inca
Increment Register AGU
Inca r0
Rx + 1 → Rx
Inca Rx
Insert
Insert Bit Field Dalu
Insert #12,#22,d6,d7
Insert #U6,#u6,Db,Dn
Insert #U6,#u6,Db,Dn
Jump If False AGU
JF lbl
JF label
JF Rn
Bit absolute long address
JFD Rn
JFD
JFD label
$00E0 $00 0000 $0000 $00 0000 002A $00 0000 001A
JMP
Jump AGU
Jmp label
JMP label
JMP label
Jump Using a Delay Slot AGU
Jmpd
Example jmpd lbl
Jmpd label
AaaaaaaaaaaaaaaaAAAAAAAAAAAAAAAAA
JSR
Jump to Subroutine AGU
Jsr r6
JSR label
Absolute long address
Example jsrd r6
Next* PC → RAS Rn → PC
Jsrd label
Jsrd Rn
Jsrd label
Jump If True AGU
Jt r0
JT label
JT Rn
JT label
Jump If True Using Delay Slot AGU
JTD
Example jtd r0
JTD label
JTD label
LPMARKx End-of-Loop Mark Prefix LPMARKx Operation
If LCn Then SAn → PC
LCn 1 → LCn Else next PC → PC → LFn If LCn Then SAn → PC
LCn 1 → LCn Else next PC → PC → LFn → SLF
Status and Conditions that Affect Lpmark Execution
Table A-17. Combinations of LPMARKx Use
LFn
LCn Description
Status and Conditions Changed by Lpmark Execution
Prefix Formats and Opcodes
Insertion of lpmarkb by assembler
Instruction Disassembled Instruction Comments
Lsll
Multiple-Bit Bitwise Shift Left Dalu
Lsll d4,d2
Lsll Da,Dn
$00E4 $0$FF 8765
LSR
Bitwise Shift Right One Bit Dalu
Lsr d4
Dn1 → Dn 0 → Dn39
Lsra
Bitwise Shift Right By One Bit AGU
Lsra r2
Rx1 → Rx 0 → Rx31
Lsrr
Multiple-Bit Bitwise Shift Right Dalu
Lsrr Da,Dn
Lsrr #u5,Dn
Lsrr d4,d2
Before After
Bit unsigned immediate data
Lsrw
Word Bitwise Shift Right Dalu
Lsrw d4,d2
Lsrw Da,Dn
Lsrw Da,Dn
MAC
Signed Fractional Multiply-Accumulate Dalu
Mac d4,d5,d6
MAC #s16,Da,Dn
Mac #$1000,d5,d6
SC140 DSP Core Reference Manual 235
Macr
Macr d4,d5,d6
RndDn ± Da.H * Db.H → Dn
Macr ±Da,Db,Dn
000 0000 0000 1000 $0008 Instruction Formats and Opcodes
238
Macsu
Macsu d0,d1,d4
Dn + Dc.H * Dd.L → Dn
Macsu Dc,Dd,Dn
111 1111 1111 1111 $FFFF Instruction Formats and Opcodes
Macus Dc,Dd,Dn
Macus
Dn + Dc.L * Dd.H → Dn
Macus Dc,Dd,Dn
Macuu
Fractional Multiply-Accumulate
Unsigned By Unsigned Dalu Operation Assembler Syntax
Macuu d2,d3,d1
Macuu Dc,Dd,Dn
PC → trace buffer
Mark
Push the PC into the Trace Buffer AGU Mark
MAX
Transfer Maximum Signed Value Dalu
Max d0,d4
If Dg Dh, then Dg → Dh
MAX2
Max2 d0,d4
If Dg.H Dh.H, then Dg.H → Dh.H
If Dg.L Dh.L, then Dg.L → Dh.L
00 D0,D4 01 D1,D5 10 D2,D6 11 D3,D7 248
MAX2VIT
If Da.L Db.L, then 0 → VFn, Da.L → Db.L
Else 1 → VFn
MAX2VIT Da,Db
Max2vit d4,d2
Maxm Dg,Dh
Maxm Transfer Maximum Absolute Value Dalu Maxm Operation
Maxm d2,d6
00 D0,D4 01 D1,D5 10 D2,D6 11 D3,D7 252
MIN
Transfer Minimum Signed Value Dalu
Min d1,d5
MIN Dg,Dh
MOVE.2F
Move Two Fractional Words from MOVE.2F
Memory to a Register Pair AGU
Description
DaDb Data Register Pairs
MOVE.2F EA,DaDb
MOVE.2L
Move.2l d0d1,r0
Da,Db ↔ EA
MOVE.2L DaDb,EA MOVE.2L EA,DaDb
Read/Write Notation
MOVE.2W
Move.2w d0d1,r0
EA ↔ DaDb
MOVE.2W EA,DaDb MOVE.2W DaDb,EA
$FF Ffff AF44
MOVE.4F
Move Four Fractional Words from MOVE.4F
Memory to a Register Quad AGU
EA → DaDbDcDd
Move.4f r0,d0d1d2d3
DaDbDcDd Data Register Quad
MOVE.4W EA,DaDbDcDd MOVE.4W DaDbDcDd,EA
MOVE.4W
EA ↔ DaDbDcDd
Move.4w d0d1d2d3,r0
MOVE.B
Byte Move AGU
Move.b d3,r7+$3
MOVE.B DR,ea
MOVE.B SP+s15,DR
MOVE.B DR,SP+s15
MOVE.B a16,DR
A32
S15
To/from Memory AGU Operation Assembler Syntax
MOVE.F
Move Fractional Word
MOVE.F Db,ea
Move.f $54,d10
MOVE.F SP+s15,Db
MOVE.F #s16,Db MOVE.F a16,Db
SC140 DSP Core Reference Manual 271
MOVE.L
Move Long Word AGU
Cccc
General Registers
#s32
#u32
MOVE.L SP+s15,De.E
MOVE.L Da.EDb.E,SP+s15
Move.l d0.ed1.e,$1224
MOVE.L SP+s15,Do.E
MOVE.L a32,De.E
MOVE.L Da.EDb.E,a32
Data Register
Da.EDb.E ff Data Register Extension Pair
278
Move Long AGU
MOVE.L a32,DR MOVE.L DR,a32
MOVE.L a16,C4 MOVE.L C4,a16
MOVE.L Rn+u3,DR MOVE.L DR,Rn+u3
MOVE.L Rn+s15,DR MOVE.L DR,Rn+s15
Move.l d0,r0
MOVE.L SP+s15,C4 MOVE.L C4,SP+s15
MOVE.L EA,DR MOVE.L DR,EA
Rrr Address Register
Read/Write Notation
Unsigned 3-bit offset
MOVE.W #s7,DR
MOVE.W #s16,C4
MOVE.W #s16,a16
MOVE.W #s16,SP-u5
Move.w #$0050,r7
MOVE.W #s7,DR MOVE.W #s16,C4
#s7
Sa16
MOVE.W
Move Integer Word AGU
MOVE.W a32,DR MOVE.W DR,a32
MOVE.W a16,C4 MOVE.W C4,a16
MOVE.W Rn+u3,DR MOVE.W DR,Rn+u3
MOVE.W Rn+s15,DR MOVE.W DR,Rn+s15
MOVE.W Rn+Rr,DR MOVE.W DR,Rn+Rr
MOVE.W Rn,C3 MOVE.W C3,Rn
Move.w d1,r7+4
MOVE.W a32,DR MOVE.W DR,a32
Write
Sss0
MOVEc Conditional Address Register Move AGU MOVEc Operation
Movet r0,r1
Movet Rq,Rn
Movef Rq,Rn
Qqq Address Register
MOVES.2F DaDb,EA
MOVES.2F Move Two Fractional Words to MOVES.2F
DaDb → EA
$7FFF $7EAC
MOVES.4F DaDbDcDd,EA
Moves.4f d0d1d2d3,r0
DaDbDcDd → EA
$7FFF
MOVES.F
Move Fractional Word to
Moves.f d0,r0
MOVES.F Db,a16
304
MOVES.L
Move Long to
Memory With Scaling and Saturation AGU Operation
Moves.l d0,r0
MOVES.L Db,EA
Memory AGU Operation Assembler Syntax
MOVEU.B
Move Unsigned Byte from
Moveu.b $0053,d10
MOVEU.B a16,DR
310
MOVEU.L
Moveu.l #$fffffff8,d3
#u32 → Db
MOVEU.L #u32,Db
31IIIIIIIIIIIIIIII16
Moveu.w #$2345,d10.l
#u16 → Db3116
#u16 → Db150
MOVEU.W #u16,Db.H
#u16
Iiiiiiiiiiiiiiii Bit unsigned immediate data
Memory to a Register AGU Operation
MOVEU.W
Move Unsigned Word from
Moveu.w r7+2,d10
MOVEU.W a16,C4
318
MPY
Mpy d4,d5,d6
Da.H * Db.H → Dn
MPY Da,Db,Dn
Mpy d6,d6,d7
SC140 DSP Core Reference Manual 321
Mpyr
Mpyr d4,d5,d6
RndDa.H * Db.H → Dn
Mpyr Da,Db,Dn
$0000
Register/Memory Address Before After L6D6
324
Mpysu
Mpysu d4,d5,d6
Dc.H * Dd.L → Dn
Mpysu Dc,Dd,Dn
326
Mpyus Dc,Dd,Dn
Mpyus
Dc.L * Dd.H → Dn
328
Mpyuu
Mpyuu d4,d5,d6
Dc.L * Dd.L → Dn
Mpyuu Dc,Dd,Dn
330
NEG
Negate Dalu
Neg d3
NEG Dn
NEG Dn
NOP
No Operation Prefix
No operation
Nop
Not
Bitwise Complement Dalu
Not d4,d5
~Da → Dn
SC140 DSP Core Reference Manual 335
~DR.L → DR.L
Binary Inversion of a 16-Bit Operand BMU
Not D0.L
Not DR.L
Memory BMU Operation Assembler Syntax
NOT.W
Binary Inversion of a 16-Bit Operand
Not.w r1
Bitwise Inclusive or Dalu
Example or d3,d0
Da Dn → Dn
Or Da,Dn
SC140 DSP Core Reference Manual 341
Or #$0f0a,d0.l
#u16 DR.L → DR.L
#u16 DR.H → DR.H
Or #u16,DR.L
Or #u16,DR.L Or #u16,DR.H
OR.W #u16,Rn
OR.W #u16,SP-u5
OR.W #u16,SP+s16
OR.W #u16,a16
Or.w #$f01a,r1
OR.W #u16,Rn
346
SP 8 → De SP 8 → SP
SP 4 → Do SP 8 → SP
POP De
POP Do
Pop d3
Eeeee
Extension Pairs, Even Registers, and Loop Start Registers
NSP 8 → De NSP 8 → ΝSP
NSP 4 → Do NSP 8 → ΝSP
Popn Do
Popn d6.ed7.e
Popn De
352
De → SP SP + 8 → SP
Do → SP + 4 SP + 8 → SP
Push De
Push Do
Push d0.ed1.e
SC140 DSP Core Reference Manual 355
De → NSP NSP + 8 → ΝSP
Do → NSP + 4 NSP + 8 → ΝSP
Pushn De
Pushn Do
Pushn d0.ed1.e
Pushn De Pushn Do
RND
Round Dalu
RndDa → Dn
RND Da,Dn
Rnd d1,d5
Rnd d2,d1
RND Da,Dn
Rol d5
Dn3801 → Dn391
Dn39 → C → Dn0
ROL Dn
ROL Dn
Ror d15
Dn39-11 → Dn38-0
→ Dn39 Dn0 → C
ROR Dn
ROR Dn
SP 4 → SR SP 8 → SP → Nmid
RTE
SP 8 → PC
Rte
Instruction Words Cycles1 Type
Rted
Example rted
Trap
RTS
Return From Subroutine AGU
Rts
If RAS valid, then RAS → PC
RTS
Rtsd
Rtsd
Rtsd
Restore PC from Stack AGU
Rtstk
Cleared
Register Address Bit Name Description EMR3
Example rtstk
SP 8 → SP
Rtstkd
SP 8 → PC
Example rtstkd
SAT.F
Sat.f d2,d3
If Da $007FFFFFFF then $007FFF0000 → Dn
SAT.F Da,Dn
SAT.F Da,Dn
SAT.L Dn
SAT.L
Sat.l d6
SC140 DSP Core Reference Manual 381
SBC
Subtract With Borrow Dalu
Db Dc C → Dd
SBC Dc,Dd
SBC Dc,Dd
SBR
Subtract And Round Dalu
Sbr d3,d0
RndDn Da → Dn
0010 1010 1110 0111 0000 0000 1000$2AE7
If LCn ≤ Then PC + displacement → PC Skipls label → LFn
Skipls
Skipls label
Skipls label
Skipls label
Enter the stop processing state
Stop
Stop Stop Instruction Processing AGU Operation
SUB
Subtract Dalu
Sub d1,d0,d2
SUB #u5,Dn
Sub d0,d1,d2
SC140 DSP Core Reference Manual 391
Sub2 d0,d1
SUB2
Subtract Two 16-Bit Values Dalu
SUB2 Da,Dn
Suba
Subtract AGU
Suba r1,r0
Suba #u5,Rx
Suba
Subl
Shift Left and Subtract Dalu
Subl d0,d1
Dn Da → Dn
$0$FF Ffff Fffe
SUBNC.W
Subnc.w #$15,d0
Dn #s16 → Dn
SUBNC.W #s16,Dn
SUBNC.W #s16,Dn
Sxt.w d3,d2
Sign-Extension Dalu
Sxt.b d3,d0
Sxt.l d3
Sxta.w r3
Sign-Extension AGU
Sxta.b r3,r1
SXTA.B
TFR
Transfer Data Register to Data Register Dalu
Tfr d15,d14
Tfr d7,d6
TFR Da,Dn
Tfra
Tfra r0,r1
Rx → Rx
Tfra rx,Rx
SC140 DSP Core Reference Manual 407
To/from a Register AGU
If Srexp = Then NSP → Rn
Else ESP → Rn If Srexp = Then Rn → NSP
Else Rn → ESP
Tfra r0,osp
Tfrt d14,d15
If T=1, then Da → Dn
If T=0, then Da → Dn
Tfrt Da, Dn
Tfrt
Trap Execute a Software Exception AGU Trap Operation
TRAPn
Trap
Tsteq
Test for Equal to Zero Dalu
Tsteq d1
If Dn == 0, then 1 → T, else 0 → T
TSTEQA.x Test for Equal to Zero AGU TSTEQA.x Operation
Tsteqa.w r4
Tsteqa.l r1
TSTEQA.W Rx
TSTEQA.W TSTEQA.L
Tstge
Test for Greater Than Or Equal to Zero Dalu
Tstge d4
If Dn = 0, then 1 → T, else 0 → T
TESTGEA.L Rx
Tstgea.l r7
If Rx ≥ 0, then 1 → T, else 0 → T
TSTGEA.L Rx
Tstgt Test for Greater Than Zero Dalu Tstgt Operation
Tstgt d6
If Dn 0, then 1 → T, else 0 → Τ
Tstgt Dn
Tstgta Test for Greater Than Zero AGU Tstgta Operation
Tstgta r2
If Rx 0, then 1 → T, else 0 → Τ
Tstgta Rx
Word Big Endian Mode
Little Endian Mode
VSL
Viterbi Shift Left Move AGU
VSL.4W D2D6D1D3,Rn+N0
VSL.4F D2D6D1D3,Rn+N0
VSL.2W D1D3,Rn+N0
VSL.2F D1D3,Rn+N0
After Big Endian
Vsl.2w d1d3,r0+n0
After Little Endian
VSL.4W
Enters the low-power standby Wait processing
Wait
State
Response
Wait
Zxt.w d3,d6
Zero Extension Dalu
Zxt.b d2,d5
Zxt.l d0
Zxta.w r4
Zero Extension AGU
Zxta.b r3,n2
ZXTA.B
ZXTA.x 432
Using the StarCore Registry
Appendix B StarCore Registry
Set Version SoC / platform
Table B-1. Scid Assignments
Hex Bits Instruction Cores Example
Index
Ecnten
Eeddef
Eselctrl 4-26ESELDI 4-26ESELDM 4-26ESELDTB 4-26 Eseletb
MOVES.F A-299 MOVES.L A-301 MOVEU.B A-307
Macsu A-239 Macus A-241 Macuu A-243
Mpysu A-325 Mpyus A-327 Mpyuu A-329
Rtstk A-374
Index
Index
SC140 DSP Core Reference Manual
