Freescale Semiconductor SC140 specifications Instruction Timing

Instruction Timing

Given the execution set in Example 5-5, the assembler adds a NOP to the object code for correct encoding.

5.3 Instruction Timing

Most of the instructions used for DSP algorithms take one cycle to execute. They can be grouped together and executed simultaneously. Other instructions, such as those used in the control portion of the application, may take more than one cycle to execute. Some of these multi-cycle instructions are change-of-flow (COF) instructions. Other control-oriented instructions use special addressing modes, or perform read-modify-write operations on memory.

Most sequential (non-change-of-flow) instructions take one cycle to execute. They include DALU, AGU arithmetic, and data moves with simple addressing modes. Data moves with address pre-calculation take two cycles, and atomic read-modify-write BMU instructions take two or three cycles.

Change-of-flow (COF) instructions take three or more cycles to execute. They include direct, PC-relative, conditional, delayed jumps and branches, and loop control instructions.

Parallel execution takes place when two or more instructions (grouped into an execution set) execute simultaneously. Instructions belonging to an execution set always start execution concurrently. A set of instructions start execution only after all the instructions belonging to previous execution sets are completed. Therefore, an execution set’s execution time is determined by the instruction in the set that has the longest execution time.

This section describes the time needed to execute SC140 instructions as measured in clock cycles. In the discussion below, it is assumed that memory accesses are zero wait-state and contention-free, unless explicitly stated otherwise. This timing is for the current SC140 implementation, and may change with future implementations.

Interrupt timing and memory access timing is also discussed in this section.

5-14 SC140 DSP Core Reference Manual