Freescale Semiconductor specifications SC140 DSP Core Reference Manual

2.2.2.1	Data Representation	2-17
2.2.2.2	Data Formats	2-18
2.2.2.3	Multiplication	2-20
2.2.2.4	Division	2-20
2.2.2.5	Unsigned Arithmetic	2-20
2.2.2.6	Rounding Modes	2-21
2.2.2.7	Arithmetic Saturation Mode	2-25
2.2.2.8	Multi-Precision Arithmetic Support	2-26
2.2.2.9	Viterbi Decoding Support	2-30
2.3	Address Generation Unit	2-31
2.3.1	AGU Architecture	2-31
2.3.2	AGU Programming Model	2-34
2.3.2.1	Address Registers (R0–R15)	2-35
2.3.2.2	Stack Pointer Registers (NSP, ESP)	2-35
2.3.2.3	Offset Registers (N0–N3)	2-36
2.3.2.4	Base Address Registers (B0–B7)	2-36
2.3.2.5	Modifier Registers (M0–M3)	2-36
2.3.2.6	Modifier Control Register (MCTL)	2-37
2.3.3	Addressing Modes	2-38
2.3.3.1	Register Direct Modes	2-38
2.3.3.2	Address Register Indirect Modes	2-38
2.3.3.3	PC Relative Mode	2-40
2.3.3.4	Special Addressing Modes	2-41
2.3.3.5	Memory Access Width	2-42
2.3.3.6	Memory Access Misalignment	2-42
2.3.3.7	Addressing Modes Summary	2-43
2.3.4	Address Modifier Modes	2-45
2.3.4.1	Linear Addressing Mode	2-45
2.3.4.2	Reverse-carry Addressing Mode	2-45
2.3.4.3	Modulo Addressing Mode	2-45
2.3.4.4	Multiple Wrap-Around Modulo Addressing Mode	2-47
2.3.5	Arithmetic Instructions on Address Registers	2-48
2.3.6	Bit Mask Instructions	2-49
2.3.6.1	Bit Mask Test and Set (Semaphore Support) Instruction	2-50
2.3.6.2	Semaphore Hardware Implementation	2-51
2.3.7	Move Instructions	2-51
2.4	Memory Interface	2-55
2.4.1	SC140 Endian Support	2-56
2.4.1.1	SC140 Bus Structure	2-56
2.4.1.2	Memory Organization	2-57
2.4.1.3	Data Moves	2-58
2.4.1.4	Multi-Register Moves	2-60
2.4.1.5	Instruction Word Transfers	2-62
2.4.1.6	Memory Access Behavior in Big/Little Endian Modes	2-64

iv SC140 DSP Core Reference Manual