Freescale Semiconductor SC140 Name Description Settings Arithmetic Saturation Mode Selects

Core Control Registers

Table 3-1. Status Register Description (Continued)

Name	Description	Settings
SM	Arithmetic Saturation Mode — Selects	0 = Arithmetic saturation mode not selected
Bit 2	automatic saturation on 32 bits for data	1 = Arithmetic saturation mode selected
	arithmetic and logic unit (DALU) results.
	This bit provides an arithmetic saturation
	mode for algorithms that do not
	recognize or cannot take advantage of
	the extension register. When the
	arithmetic saturation mode is set, the
	scaling mode bits are ignored for most
	instructions. No scaling is performed.
	Refer to Section 2.2.2.7, “Arithmetic
	Saturation Mode,” on page 2-25, for
	details of arithmetic saturation, including
	the list of instructions affected by
	arithmetic saturation with or without
	scaling.
	Each individual instruction in
	Appendix A, “SC140 DSP Core
	Instruction Set,” lists arithmetic
	saturation as a condition, if appropriate.
	This bit is cleared at core reset.
T	True Bit — Indicates whether the	0 = Condition tested by compare or test instruction is false
Bit 1	condition being tested by a compare or	1 = Condition tested by compare or test instruction is true
	test instruction is true or false.
	The T-bit is affected by all instructions
	that check a condition, such as CMPxx,
	TSTxx, and BMTSTx. The BMTSET.W
	instruction also sets this bit if a write to
	memory fails. Conditional instructions
	(such as JT, JF, BT, BF, IFT, and others)
	test the T-bit, and execute accordingly.
	This bit is cleared during core reset as
	well as at the start of an exception
	service routine.

3-6 SC140 DSP Core Reference Manual