Freescale Semiconductor SC140 specifications DREE3

EOnCE Controller Registers

	Table 4-14. ESR Description (Continued)
Name	Description
DREE3	Debug Reason is EE3 — Set when the core enters debug state or executes a
Bit 13	debug exception as a result of EE3 assertion. It is cleared by the EOnCE when the
	core exits debug state, or when the DIS bit in EMCR is reset by the user.
DREE2	Debug Reason is EE2 — Set when the core enters debug state or executes a
Bit 12	debug exception as a result of EE2 assertion. It is cleared by the EOnCE when the
	core exits debug state, or when the DIS bit in EMCR is reset by the user.
DREE1	Debug Reason is EE1 — Set when the core enters debug state or executes a
Bit 11	debug exception as a result of the EE1 assertion. It is cleared by the EOnCE when
	the core exits debug state, or when the DIS bit in EMCR is reset by the user.
DREE0	Debug Reason is EE0 — Set when the core enters debug state or executes a
Bit 10	debug exception as a result of EE0 assertion. It is cleared by the EOnCE when the
	core exits debug state, or when the DIS bit in EMCR is reset by the user.
DRCOUNTER	Debug Reason is Counter — Set when the core enters debug state or executes a
Bit 9	debug exception as a result of a count event. It is cleared by the EOnCE when the
	core exits debug state, or when the DIS bit in EMCR is reset by the user.
DREDCAD	Debug Reason is EDCD — Set when the core enters debug state or executes a
Bit 8	debug exception as a result of detection by the EDCD. It is cleared by the EOnCE
	when the core exits debug state, or when the DIS bit in EMCR is reset by the user.
DREDCA7	Debug Reason is EDCA7 — Set when the core enters debug state or executes a
Bit 7	debug exception as a result of detection by the optional external EDCA7. It is
	cleared by the EOnCE when the core exits debug state, or when the DIS bit in
	EMCR is reset by the user.
DREDCA6	Debug Reason is EDCA6 — Set when the core enters debug state or executes a
Bit 6	debug exception as a result of detection by the optional external EDCA6. It is
	cleared by the EOnCE when the core exits debug state, or when the DIS bit in
	EMCR is reset by the user.
DREDCA5	Debug Reason is EDCA5 — Set when the core enters debug state or executes a
Bit 5	debug exception as a result of detection by EDCA5. It is cleared by the EOnCE
	when the core exits debug state, or when the DIS bit in EMCR is reset by the user.
DREDCA4	Debug Reason is EDCA4 — Set when the core enters debug state or executes a
Bit 4	debug exception as a result of detection by EDCA4. It is cleared by the EOnCE
	when the core exits debug state, or when the DIS bit in EMCR is reset by the user.
DREDCA3	Debug Reason is EDCA3 — Set when the core enters debug state or executes a
Bit 3	debug exception as a result of detection by EDCA3. It is cleared by the EOnCE
	when the core exits debug state, or when the DIS bit in EMCR is reset by the user.
DREDCA2	Debug Reason is EDCA2 — Set when the core enters debug state or executes a
Bit 2	debug exception as a result of detection by EDCA2. It is cleared by the EOnCE
	when the core exits debug state, or when the DIS bit in EMCR is reset by the user.
DREDCA1	Debug Reason is EDCA1 — Set when the core enters debug state or executes a
Bit 1	debug exception as a result of detection by EDCA1. It is cleared by the EOnCE
	when the core exits debug state, or when the DIS bit in EMCR is reset by the user.
DREDCA0	Debug Reason is EDCA0 — Set when the core enters debug state or executes a
Bit 0	debug exception as a result of detection by EDCA0. It is cleared by the EOnCE
	when the core exits debug state, or when the DIS bit in EMCR is reset by the user.

4-40 SC140 DSP Core Reference Manual