EOnCE Module Internal Architecture

Reading and writing EOnCE registers from the software

Real-time JTAG port access

Real-time data transfer

Executing instructions while in debug state

Samples core PC information in various states

Figure 4-8 displays the EOnCE controller block diagram.

TCK

 

 

 

 

 

Command Register

6

0

Status Register

 

 

Address

 

 

 

 

Monitor and Control Register

TDI

Address

 

 

Control

 

Decoder

 

 

Logic

 

 

 

 

 

Receive Register

 

 

 

TDO

Transmit Register

 

 

 

 

 

 

 

Update Signal from the TAP Controller

 

 

 

Figure 4-8. EOnCE Controller Block Diagram

The EOnCE controller register set is shown in Table 4-6.

Table 4-6. EOnCE Controller Register Set

Register Name

Description

 

 

 

 

ECR

EOnCE command register

 

 

ESR

EOnCE status register

 

 

EMCR

EOnCE monitor and control register

 

 

ERCV

EOnCE receive register

 

 

ETRSMT

EOnCE transmit register

 

 

EE_CTRL

EE signals control register

 

 

CORE_CMD

EOnCE core command register

 

 

PC_EXCP

PC of the execution set causing illegal or overflow exception

 

 

SC140 DSP Core Reference Manual

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Freescale Semiconductor SC140 specifications Command Register, Address Monitor and Control Register