Freescale Semiconductor SC140 specifications Instruction Pre-Fetch and Fetch, Instruction Dispatch

Pipeline

5.1.1.1 Instruction Pre-Fetch and Fetch

The first two stages of the pipeline are the pre-fetch and fetch stages. These two stages combined are responsible for the program memory read of the fetch set. Each fetch set contains eight instruction words.

In the pre-fetch stage, the address of the fetch set is driven into the program address bus (PAB) along with the read strobe. This enables the memory read process. While the address is issued to memory, the fetch counter (FC) in the PSEQ is updated for the next program memory read. Both of these operations occur in parallel. The address can be generated by the PSEQ for:

•Normal program flow

•Exception program flow

•Hardware loops

•Change-of-flow instructions in the AGU

The fetch stage, which follows the pre-fetch stage, is dedicated to waiting for the memory access to be completed. Memory access is completed when the PSEQ samples the program memory value from the 128-bit wide program data bus (PDB).

Since an execution set can overlap to a second fetch set, more than one fetch set is stored in a buffer. However, the instructions in an execution set need to be dispatched together.

The SC140 core in the current implementation holds an internal fetch buffer of 4 fetch sets (128 bits each). VLES are dispatched form this buffer to the execution units, emptying the buffer. Dispatching is unrelated to fetching, and only the actual number of instruction words needed for execution are dispatched. Hence a single fetch set can be "consumed" anywhere between 1 cycle (in case the VLES is 8 words long) and 8 cycles (in case it contains 8 VLES of 1 word each). The fetch unit tries to keep this buffer full as much as it can. After reset and after every change of flow (COF), a series of 4 fetch requests is issued to the memory. Upon dispatch of the last instruction in the fetch set, another fetch request is issued to the memory. In serial code it means that a fetch is issued between once per cycle and once every 8 cycles, depending on the width of the VLES that are executed. Hence the main factors that affect the density of fetches on the program bus are the width of the execution set (number of instructions per set - affects the rate the buffer is emptied) and the frequency of COF instructions (which trigger a fetch buffer flush and re-fill).

5.1.1.2 Instruction Dispatch

After the fetch set is read from memory to the PSEQ, the PSEQ detects which instructions are grouped into an execution set. These instructions will be dispatched in parallel such that the number of cycles taken by the longest instruction will determine the number of cycles for the whole execution set. The PSEQ detects the type of instructions (such as DALU or AGU), and the AGU instructions are decoded.

5.1.1.3 Address Generation

The address generation pipeline stage is implemented in the AGU and DALU. In the DALU, the address generation stage includes decoding the DALU instructions. However, in the AGU, the address generation stage includes updating the address pointers as well as the actual memory accesses (driving the address and the read/write strobes). The AGU is also responsible for address calculation when a change-of-flow operation takes place.

5-4 SC140 DSP Core Reference Manual