Freescale Semiconductor SC140 specifications Debugerst

EOnCE Controller Registers

	Table 4-15. EMCR Description (Continued)
Name	Description
DEBUGERST	Debugger Status Information — If several applications (debugger processes) try
Bits 21–18	to connect to the core, unaware of each other, DEBUGERST bits serve as flags.
	Reset once the core is powered, they can be set/reset by the application as an
	occupy signal. The debugger may use these bits to reserve the core for its use.
	In case the host disconnects from the core or goes down, when the host
	(debugger) tries to regain control on the core, it can use the DEBUGERST bits to
	find out at when the host disconnected. This is extremely useful when the host is
	connected to the core through a network rather than direct cables.
SWDIS	Software Access Disable — Enables the debug host to lock the EOnCE. When
Bit 17	the bit is set, software write access is denied to all the EOnCE registers except the
	ETRSMT register. Software read access is denied from the trace buffer.
IME	Interrupt Mode Enable — When set, this bit causes the core to execute a debug
Bit 16	exception instead of entering debug state for any of the source events that would
	have put the core in debug state. This bit can only be changed when all debug
	request sources are disabled, specifically when there are no debug requests from
	the external source (JTAG port, EE pin or system debug request), trace buffer,
	event selector or from the execution of a debug instruction.
	Debug request signals from external sources should not normally be used as a
	source for debug exceptions. If they are used, the interrupt request should be kept
	asserted until the core acknowledges it to the driver by some agreed SW protocol.
	The core then must acknowledge that the interrupt was de-asserted before the
	driver may assert it again.
DIS	Debug Interrupt Status — Sticky bit that is set by the EOnCE when a debug
Bit 15	exception is generated. When a user resets this bit, all the debug reason bits of the
	ESR are reset.
R	Reserved
Bits 14–9
EDCDST	EDCD Status — Sticky bit that is set by the EOnCE upon event detection by the
Bit 8	EDCD. Should be cleared by the user.
EDCAST7	EDCA7 Status — Sticky bit that is set by the EOnCE upon event detection by the
Bit 7	optional external EDCA7. It should be cleared by the user.
EDCAST6	EDCA6 Status — Sticky bit that is set by the EOnCE upon event detection by the
Bit 6	optional external EDCA6. It should be cleared by the user.
EDCAST5	EDCA5 Status — Sticky bit that is set by the EOnCE upon event detection by
Bit 5	EDCA5. It should be cleared by the user.
EDCAST4	EDCA4 Status — Sticky bit that is set by the EOnCE upon event detection by
Bit 4	EDCA4. It should be cleared by the user.
EDCAST3	EDCA3 Status — Sticky bit that is set by the EOnCE upon event detection by
Bit 3	EDCA3. It should be cleared by the user.
EDCAST2	EDCA2 Status — Sticky bit that is set by the EOnCE upon event detection by
Bit 2	EDCA2. It should be cleared by the user.
EDCAST1	EDCA1 Status — Sticky bit that is set by the EOnCE upon event detection by
Bit 1	EDCA1. It should be cleared by the user.
EDCAST0	EDCA0 Status — Sticky bit that is set by the EOnCE upon event detection by
Bit 0	EDCA0. It should be cleared by the user.

4-42 SC140 DSP Core Reference Manual