Freescale Semiconductor SC140 specifications Prefix Types, Two-Word Prefix

Instruction Grouping

5.2.2 Prefix Types

The SC140 architecture supports 2 types of prefix instructions, each is used to convey a subset or all of the following information about the VLES:

•The number of instructions that are grouped together in the execution set.

•Conditional execution of the whole set or a subgroup of the set (encoding the IFT/IFF/IFA prefix instructions).

•Looping information for supporting hardware loops (encoding the LPMARKA and LPMARKB bits).

•Encoding extensions for high register banks (D8-D15, R8-R15).

The prefix instructions use either one or two instruction words. Since the fetch set is eight words long, and the maximum issue width is six (four DALU instructions and two AGU instructions), there is usually room for two prefix words without affecting performance. However, in order to save code size, 3 prefix instruction types were defined. Two one-word prefix types have a subset of the mentioned functionality. A two-word prefix has all of the listed functionality. The selection of the right prefix type is done by the assembler which automatically chooses the smallest prefix type (or no prefix at all); see Figure 5-3.

The detailed encoding for prefix words is specified in Appendix A.1.5, “Prefix Word Encoding.”

5.2.2.1 Two-Word Prefix

The two-word prefix includes all information that could be specified in a prefix:

•Number of instructions in the VLES

•Mark hardware loop information

•Specify conditional execution of the VLES or sub-groups of the VLES

•Encode high register banks (D8-D15, R8-R15)

The SC140 16-bit instruction encoding has a three bit field for specifying each data register or address pointer register. On their own, these instructions can encode eight DALU registers (D0–D7) and eight address pointers (R0–R7). In order to specify operands that belong to the high register banks (D8–D15, and R8–R15), additional register field bits are encoded in a second prefix word.

The two-word prefix includes a register field for each execution unit in the core (namely, four fields for DALU instructions and two fields for AGU instructions). At most, DALU instructions have three operands (for example, ADD D0,D1,D2). Therefore, each DALU field is three bits, so that each operand can be independently specified to be in the high bank. Most AGU instructions have two operands (for example, MOVE (R0)+,D0). Therefore, each AGU field has two bits.

A register extension bit is added for each possible operand in each execution unit. If this bit is set, it signifies that the respective operand uses a register from the high bank. If this bit is cleared, or if the respective set does not include a two-word prefix, the operand uses a register from the low bank. A two-word prefix is generated by the assembler if at least one of the instructions in the execution set uses a register from the high bank.

For a description of what conditional execution options are available, see Section 5.2.3, “Conditional Execution.”

For a description about the function of HW loop support with LPMARK, see Section 5.4, “Hardware Loops.”

5-8 SC140 DSP Core Reference Manual