Exception Processing

 

 

 

 

 

 

 

 

 

Table 5-19. Exception Vector Address Table

 

 

Exception Address

Priority

Type

Description

 

 

Offset

(0 - highest)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0x00

0

TRAP

TRAP instruction

 

 

 

 

 

 

 

 

0x40

-

Reserved

 

 

 

 

 

 

 

 

 

0x80

1

ILLEGAL

ILLEGAL instruction, and illegal

 

 

 

 

 

instruction set

 

 

 

 

 

 

 

 

0xC0

2

DEBUG

DEBUG exception from EOnCE

 

 

 

 

 

 

 

 

0x100

3

Overflow

DALU overflow

 

 

 

 

 

 

 

 

0x140

-

Reserved

 

 

 

 

 

 

 

 

 

0x180

5

Auto-NMI

NMI default vector

 

 

 

 

 

 

 

 

0x1C0

6

Auto-IR

Interrupt default vector

 

 

 

 

 

 

 

 

0x200-0xFC0

5

NMI

NMI

 

 

 

 

 

 

 

 

External interrupts

External interrupts

 

 

 

 

 

 

 

 

 

 

 

5.8.2 Return From Exception Instructions

Return from exception should be done with dedicated Return from Exception instructions (RTE, RTED, - termed collectively “RTE-like” instructions). These instructions pop from the active stack two values: The return PC, form which execution resumes, and SR value. The SR value sets (among other things) the working mode of the core. The RTE-like instructions are used to automatically enable resuming the task that was interrupted (by restoring the next PC to be executed and the SR, including the working mode). It could also be manipulated by the RTOS to change the task that is restored.

For maximum efficiency on return from an exception, the SC140 instruction set provides a delayed return from the exception instruction. This takes five or six cycles to execute, but allows the usage of some of these cycles to execute instructions. Refer to Appendix A, “SC140 DSP Core Instruction Set,” for details on return-from-exception usage in the RTE and RTED instructions.

The RTE/D instructions do not affect the shadow return address of subroutines, see Section 5.5.5, “Fast Return from Subroutines.” In this way, the interrupts interfere less with the interrupted task, allowing it to continue and enjoy the reduced cycle count when performing an RTS, if applicable. However, if during the ISR, the task was switched, the RAS may hold content from the previous task that may corrupt the execution of the restored task. In such a case, the user should clear the RAS by performing, in the ISR that switches the tasks, a dummy jump to subroutine (JSR) and return (RTS). .

SC140 DSP Core Reference Manual

5-49

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Image 229
Freescale Semiconductor SC140 specifications Return From Exception Instructions, Exception Vector Address Table