Freescale Semiconductor SC140 Overflow Exception Enable Bit, Disable Interrupts Bit When this bit

Core Control Registers

Table 3-1. Status Register Description (Continued)

Name	Description	Settings
OVE	Overflow Exception Enable Bit —	0	= Overflow exception generation is disabled
Bit 20	Enables or disables the generation of an	1	= Overflow exception generation is enabled, unless DOVF
	exception caused by an overflow. The		bit in EMR is already 1
	DOVF bit in EMR is always set when an
	overflow occurs. If the OVE bit is set and
	the DOVF bit is already set, no exception
	is generated until the DOVF bit is cleared
	and set again.
	See Section 3.1.2, “Exception and Mode
	Register (EMR),” for more information.
	This bit is cleared at core reset.
DI	Disable Interrupts Bit — When this bit	0	= Interrupts enabled
Bit 19	is set, no maskable interrupts are	1	= Interrupts disabled
	serviced, regardless of the IPL values,
	which remain unchanged.
	This bit can be set with the DI instruction,
	which ensures that interrupts are
	masked immediately, and can be cleared
	with the EI instruction.
	This bit is cleared at core reset.
EXP	Exception Mode Bit — Selects the	0	= Normal working mode, active SP is NSP
Bit 18	active stack pointer and working mode of	1	= Exception working mode, active SP is ESP
	the core.
	This bit is set at core reset.
R	Reserved
Bits
17–12
VF3–VF0	Viterbi Flags — Reflect the status of the	0	= Appropriate 16-bit portion transferred
Bits 11–8	two parallel conditional transfers in the	1	= Appropriate 16-bit portion not transferred
	MAX2VIT instruction. These flags are
	generally used in conjunction with the
	VSL instructions. Two Viterbi flags can
	be independently set or cleared
	according to the MAX2VIT result.
	For more information, see MAX2VIT and
	VSL in Appendix A, “SC140 DSP Core
	Instruction Set.”
	These bits are cleared at core reset.

RReserved

Bit 7

3-4 SC140 DSP Core Reference Manual