Freescale Semiconductor SC140 Implicit Push/Pop Memory Timing, Memory Stall Conditions

Instruction Timing

Example 5-11 shows the parallel execution of a bit mask and a pop instruction. The example distinguishes the cases of a valid and invalid shadow SP (see Section 5.5.4, “Shadow Stack Pointer Registers.” )

If the shadow SP is not valid as in Case A (meaning the address of the stack pointer was overwritten), the address of the stack pointer (SP–8) must be pre-calculated from the value in SP. There is no contention since the two read operations occur at different cycles.

If the shadow SP is valid as in Case B, the address of the stack pointer that was saved in the shadow SP is readily available. Cycle 1 now includes two reads that may access the same location and may cause contention.

Example 5-11. Execution Set Containing a Bit Mask and a Pop Instruction

A)

BMTSTS.W #$0800,(R0)	POP D0
;Shadow SP is not valid, R0==SP-8
;Cycle 1: read from (R0)
;Cycle 2: read from (SP-8)
B)
BMTSTS.W #$0800,(R0)	POP D0
;Shadow SP is valid

;Cycle 1: read from (R0); read from (SP-8)

5.3.3.2 Implicit Push/Pop Memory Timing

Instructions with implicit push/pop memory access (such as JSR and RTE) execute the memory access after all other accesses in the execution set have been performed.

Delayed instructions with implicit push memory access (such as JSRD) access memory after all other accesses in the delay slot have been performed. Delayed instructions with implicit pop memory access (such as RTSD and so on) access memory before accesses in the delay slot are performed.

Consequently, these instructions do not cause contention when they are executed in parallel with other instructions that access memory.

5.3.3.3 Memory Stall Conditions

The SC140 can generate up to three memory accesses per cycle consisting of one program fetch and two data accesses. The extent to which the specific memory configuration can support various kinds of simultaneous accesses to memory modules may vary from chip to chip. The memory system identifies access combinations (usually by means of a bus controller) that cannot be supported simultaneously. The memory system stalls the SC140, which results in the serialization of the contending accesses. For example, a stall occurs when a memory unit that can support only one access at a time receives a simultaneous request for two data accesses (or for one program access and one data access). Stalls can also occur if the memory itself is not zero-wait-states, which may be a characteristic of the memory technology (such as flash or DRAM), or may occur with off-chip memory.

5-24 SC140 DSP Core Reference Manual