Freescale Semiconductor SC140 specifications TAP Controller State Machine Jtag Scan Paths

Overview of the Combined JTAG and EOnCE Interface

TMS=1

Test-Logic-Reset

TMS=0	TMS=0	TMS=1
				TMS=1			TMS=1
	Run-Test/Idle		Select-DR-Scan			Select-IR-Scan
			TMS=0			TMS=0
		TMS=1	Capture-DR		TMS=1	Capture-IR
			TMS=0	TMS=0		TMS=0	TMS=0
			Shift-DR			Shift-IR
			TMS=1			TMS=1
			Exit1-DR			Exit1-IR
			TMS=0 TMS=0			TMS=0 TMS=0
			Pause-DR			Pause-IR
			TMS=1			TMS=1
		TMS=0	Exit2-DR		TMS=0	Exit2-IR
			TMS=1		TMS=1	TMS=1	TMS=1
			Update-DR			Update-IR
		TMS=1			TMS=1
			TMS=0			TMS=0

Figure 4-2. TAP Controller State Machine

Table 4-3. JTAG Scan Paths

Select-DR Scan Path	Select-IR Scan Path
Select-DR_SCAN	Select-IR_SCAN
Capture-DR	Capture-IR
Shift-DR	Shift-IR
Exit1-DR	Exit1-IR
Update-DR	Update-IR

At power-up or during normal operation of the host, the TAP is forced into the Test-Logic-Reset state when the TMS signal is driven high for five or more Test Clock (TCK) cycles.

When test access is required, TMS is set low to cause the TAP to exit the Test-Logic-Reset and move through the appropriate states. From the Run-Test/Idle state, an instruction register scan or a data register scan can be issued to transition through the appropriate states.

SC140 DSP Core Reference Manual 4-5