Freescale Semiconductor SC140 specifications Grouping rules for explicit Isap instructions

Programming Rules

6.8.2 Grouping rules for explicit ISAP instructions

G.G.2: up to 8 instruction words per VLES

G.G.3: One ISAP encoding word per VLES

G.G.4: A destination operand can only be updated by one source per VLES. In the context of the ISAP, it means the following limitations:

•The same core register being updated by the ISAP and another core or ISAP instruction

•A core address register updated by an implicit AGU instruction generated for supporting and ISAP instruction, and the same address register being updated by another instruction.

•The T bit being updated by the ISAP and another core or ISAP instruction

G.P.8: It is not allowed to group AGU instructions that use or update a data register (D0-D15) in the same VLES with an ISAP instruction.

G.P.9: ISAP ALU instructions must belong to the same IFc condition group.

6.8.3 Rules for implicit AGU instructions

As mentioned in Section 6.4, “ISAP Memory Access,” on page 6-60, when a data transfer instruction between the ISAP and the memory or core register is written inside the ISAP brackets, the core assembler creates an implicit MOVE instruction that will send the required address to the data memory.

The ramification of this is that when there is a MOVE-like instruction inside the ISAP brackets, all the rules that apply for “original core” MOVE-like instructions apply for the implicit MOVE-like instructions as well.

An example from Rule A.2, for an ISAP instruction, is shown below:

Example 6-8. MOVE rules with an implicit MOVE instruction from ISAP

The original rule requires (among other cases) a cycle difference between a MOVE-like instruction to an R register and it’s use as an AAU operand (see Rule A.2 on page 7-17):

core_ins {move.l k0,r0}	;core instruction, with ISAP move instruction
adda r0,r1	;not allowed

This is so because the core assembler generates the implicit MOVE instruction. In the example above, the effective assembler code for the first line will look like:

core_ins move.l d0,r0 {move.l k0,bus}		;not allowed
jmp	r0

Where the core ignores its own d0 part of the implicit move instruction. As can be seen, Rule A.2 prohibits this.

In a manner similar to the one shown, the following rules are relevant also to implicit AGU instructions:

G.G.5, G.P.1, G.P.4, G.P.5, G.P.6, A.1, A.2, A.4, T.1, SR.2, A.2a, A.5, A.6, D.7, A.1a.

6-68 SC140 DSP Core Reference Manual