Freescale Semiconductor SC140 specifications Xiv

4-7	Software Downloading	4-13
4-8	EOnCE Controller Block Diagram	4-17
4-9	Event Counter Block Diagram	4-19
4-10	Event Detection Unit Block Diagram	4-21
4-11	EDCA Block Diagram	4-22
4-12	EDCD Block Diagram	4-24
4-13	Event Selector Block Diagram	4-26
4-14	Trace Unit Block Diagram	4-28
4-15	EOnCE Command Register (ECR)	4-36
4-16	EOnCE Status Register (ESR)	4-38
4-17	EOnCE Monitor and Control Register (EMCR)	4-41
4-18	EE Signals Control Register (EE_CTRL)	4-45
4-19	Injected Instruction Format	4-48
4-20	Event Counter Register (ECNT_CTRL)	4-51
4-21	EDCA Control Register (EDCAi_CTRL)	4-54
4-22	EDCD Control Register (EDCD_CTRL)	4-58
4-23	Event Selector Control Register (ESEL_CTRL)	4-62
4-24	Event Selector Mask Debug State (ESEL_DM)	4-63
4-25	Event Selector Mask Debug Exception (ESEL_DI)	4-64
4-26	Event Selector Mask Enable Trace (ESEL_ETB)	4-64
4-27	Event Selector Mask Disable Trace (ESEL_DTB)	4-65
4-28	Trace Buffer Control Register (TB_CTRL)	4-67
5-1	Instruction Pipeline Stages	. 5-2
5-2	Instruction Grouping Methods	. 5-6
5-3	Low Register Prefix Selection Algorithm	5-11
5-4	Hardware Loop Programming Model	5-25
5-5	Loop Nesting	5-28
5-6	SC140 Memory Use with a Single Stack Pointer	5-32
5-7	SC140 Memory Use with Dual Stack Pointers	5-33
5-8	Working mode Transitions - Unprotected Dual-stack RTOS	5-38
5-9	Working mode Transitions - Unprotected Single-stack RTOS	5-39
5-10	Core State Diagram	5-42
5-11	Core-PIC Interface	5-47
5-12	Flowchart for Exception Timing	5-55
6-1	Core to Single ISAP Connection Schematic	6-58
6-2	Core to Multiple ISAP Connection Schematic	6-59

xiv SC140 DSP Core Reference Manual